• Corelogic, Inc. v. Boundary Solutions, Inc.All claims unpatentable
  PTAB · May 19, 2016 · IPR2015-00226 · APJ Peter P Chen · IPR · Final written decision

  Claims 1–12, 14, 15, and 19–21 are unpatentable as obvious over the Harder-based grounds; the Kearney and ARC/INFO ground was not proven for claims 1–6 and 20–21.

  RulingsFinal written decision

  • BurdenFwd mixedUnpatentable

    “In summary, we agree with Petitioner’s contentions and find that Harder and Longley, once combined as proposed by Petitioner, teach or suggest the limitations of independent claim 1.” slip op. at 20

  • Skill levelSkill level board ownOther

    “C. Level of Ordinary Skill in the Art Petitioner’s proposal for the level of ordinary skill in the art is “at least a bachelors degree in geographic information science, survey engineering, geomatics, or similar education, and two years of experience in a relevant field (e.g., land or geographic information science), or six years of experience in the relevant field.” Ex. 1006 (Declaration of Michael Goodchild), ¶ 11. Patent Owner has proposed that one of ordinary skill in the art would possess a “a Bachelor’s degree or higher in, GIS engineering with at least 5 years of academic or industry experience in GIS database design..” Ex. 2005 (Declaration of William Huxhold), ¶ 14. We determine that an express definition of the level of ordinary skill is not required. The level of ordinary skill in the art can be reflected in the cited prior art references. See Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001) (“[T]he absence of specific findings on the level of skill in the art does not give rise to reversible error where the prior art itself reflects an appropriate level and a need for testimony is not shown.”) (internal quotations omitted); In re GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995). Therefore, we find the level of ordinary skill in the art to be reflected in the cited references.” slip op. at 11

  • Obviousness (§103) › Motivation to combine / reasonable expectation of successMotivation foundDecided for petitioner

    “The disclosure of Longley and the knowledge of one skilled in the art would have motivated such a person to modify Harder’s system given that Harder discloses parcel-based searching and display functionalities for a jurisdiction (e.g., Ex. 1003, 21-25) and for multiple states (id., 49-51), and discloses that databases in GIS environments could span multiple jurisdictions (id.,7, 49- 51), and that Longley discloses configuring such databases to include data relating to different states and also discloses parcel based systems. Moreover, one skilled in the art would have been motivated to look to Longley to supplement the features of the systems and processes of Harder given they both describe[] features of ESRI systems. Ex. 1015, 170, 172; Ex. 1003. Thus, modifying Harder’s database in such a way would have been a common sense and predictable modification that was within the realm of knowledge of one skilled in the art at the time of the alleged invention. See KSR, 550 U.S. at 417; Ex. 1006, ¶¶ 35- 39. Pet. 18–19. The Petition continues:” slip op. at 20

  • Obviousness (§103) › Graham factors (scope of art, differences, level of skill)UnpatentableUnpatentable

  Patent outcomesUS 7,499,946 unpatentable
  § 103 obviousnesscites KSR · Graham
  Patents in suitUS 7,499,946
• Corelogic, Inc. v. Boundary Solutions, Inc.All claims unpatentable
  PTAB · May 19, 2016 · IPR2015-00222 · APJ Lynne E Pettigrew · IPR · Final written decision

  Claims 1–23 are unpatentable: claims 9, 10, and 12–22 as obvious over Harder and Du; claims 1–8, 11, and 23 as obvious over Harder, Du, and MacDonald.

  RulingsFinal written decision

  • Skill levelSkill level board ownDecided for petitioner

    “We determine that an express definition of the level of ordinary skill is not required. The level of ordinary skill in the art can be reflected in the cited prior art references. See Okajima, 261 F.3d at 1355 (“[T]he absence of specific findings on the level of skill in the art does not give rise to reversible error where the prior art itself reflects an appropriate level and a need for testimony is not shown.” (internal quotations omitted)); In re GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995). In this case, we find the level of ordinary skill in the art to be reflected in the cited references.” slip op. at 14

  • Claim Construction › Intrinsic evidence (Phillips canons) › Plain and ordinary meaning to a POSITATerm construed petitioner constructionDecided for petitioner

    “We remain unpersuaded by BSI’s arguments. As we explained in the Institution Decision, although the ’352 patent describes assembling a national parcel-level map database from data provided by various sponsoring agencies, the claims themselves do not require assembling the multi-jurisdictional database using any specific method or obtaining the information in the database from any particular sources. Dec. 7 (citing Ex. 1001, 1:41–48, 4:8–11). Moreover, BSI’s reliance on the prosecution history of the ’957 patent does not support its position, as the claims at issue there did not recite a “multi-jurisdictional database.” See Ex. 2006, 132–37, 141, 193–200). For these reasons, we maintain our construction of “multi- jurisdictional database” as “a collection of data relating to two or more jurisdictions.”” slip op. at 8

  • Obviousness (§103) › Motivation to combine / reasonable expectation of successMotivation foundReasonable expectation foundUnpatentable

    “success”9 in combining Harder and Du because Du would not be used to maintain data for jurisdictions with a large number of parcels, and the visibility of parcels would be diminished in a map with so many parcels. PO Resp. 38. We do not find this argument to be persuasive because, as CoreLogic notes, Du discloses that cells can correspond to different types of jurisdictions and that any geographic areas can be searched and displayed. See Reply 14 (citing Ex. 1018, Fig. 3, 3:21–32, 4:38–40, 6:31–38, 9:5–6, 9:16–44). BSI also argues that a county identified as a cell in Du would include a huge amount of parcel data, and data for the entire cell would be transmitted to a client computer in the system described in Du, thereby defeating a purpose of Du’s system—the speedy display of maps. PO Resp. 38–39. CoreLogic, however, relies on Du for teaching an index of 9 We understand BSI’s use of the phrase “reasonable likelihood of success” to be an argument that there would be no “reasonable expectation of success” in the combination of references, rather than a reference to the reasonable likelihood standard for instituting an inter partes review. jurisdictional identifiers used to search a portion of a multi-jurisdictional database, not the transmission of parcel data, and has shown sufficiently that a person of ordinary skill in the art would have combined Du’s teaching of an index with Harder’s system for retrieving and transmitting parcel boundary polygon map data. See Reply 15. We have reviewed the parties’ arguments and evidence on this issue, and we agree with and adopt CoreLogic’s reasoning for modifying Harder’s single-county example in view of Du to retrieve a jurisdictional identifier from an index and use it to search a portion of a multi-jurisdictional database for a selected parcel. In sum, we find that the combination of Harder and Du teaches or suggests the limitations of claim 9 and that CoreLogic has provided articulated reasoning supported by rational underpinnings for combining the references in the manner asserted. Therefore, we conclude CoreLogic has shown by a preponderance of the evidence that claim 9 would have been obvious over Harder and Du.” slip op. at 22

  • ExcludeMotion to exclude, deniedDenied

    “G. CoreLogic’s Motion to Exclude Evidence CoreLogic moves to exclude the redirect testimony of BSI’s expert, Mr. William Huxhold, on the ground that it was provided in response to leading questions. Mot. Excl. 1 (citing Ex. 1034, 150:6–153:8). The redirect testimony relates to a portion of Mr. Huxhold’s cross-examination testimony. Id. at 1–2 (citing Ex. 1034, 72:5–22). Because we do not rely on the cited redirect testimony or the cited cross-examination testimony, CoreLogic’s motion is dismissed as moot.” slip op. at 40

  Patent outcomesUS 8,065,352 unpatentable
  Claim construction§ 103 obviousnesscites KSR · Graham
  Patents in suitUS 8,065,352
• Corelogic, Inc. v. Boundary Solutions, Inc.All claims unpatentable
  PTAB · May 19, 2016 · IPR2015-00228 · APJ Peter P Chen · IPR · Final written decision

  Claims 1–12, 14, 15, and 19 are unpatentable: claims 1–10, 12, 14, 15, and 19 as obvious over Harder and Longley, and claim 11 over Harder, Longley, and Roy.

  RulingsFinal written decision

  • Claim Construction › Intrinsic evidence (Phillips canons) › Plain and ordinary meaning to a POSITATerm construed board ownDecided for petitioner

    “In our Decision to Institute, we construed “numerical jurisdictional identifier” to mean “a number that identifies a jurisdiction.” Dec. to Inst. 7– 8. We based our construction on the only appearance of “jurisdictional identifier” in the written description of the ’957 patent: FIG. 3 illustrates a USA County Boundary Map (USACM). This is a public domain boundary file of each and every of the 3140 counties within the United States. Each of these polygons is 8 geocoded with its county name and FIPS number, a numerical jurisdictional identifier, as illustrated in the figure. Ex. 1001, 8:48–53 (emphasis added).1 Patent Owner does not challenge our construction of “jurisdictional identifier” in its Patent Owner Response, see PO Resp. 7, nor does Petitioner challenge the construction in its Reply, see Reply 7. For this Final Written Decision, after considering the complete record, we maintain our construction of “numerical jurisdictional identifier” as “a number that identifies a jurisdiction.”” slip op. at 8

  • Claim Construction › Threshold & procedure › Whether a term needs construction (O2 Micro)No construction neededDecided for petitioner

    “Patent Owner also proposes a construction for “national parcel map database comprising multiple jurisdictional databases which have been normalized to a common data protocol.” PO Resp. 7–15. Patent Owner’s proposal is 60 words long, and reads, “a database covering more than one state including multiple jurisdictional databases, wherein a jurisdictional database is a collection of data representing the boundaries of parcels from the jurisdiction, each of the jurisdictional databases having been received from a jurisdiction, and modified, transformed, amended or converted by a common set of one or more processes applied to all data and updates.” PO Resp. 8. Patent Owner had in its Preliminary Response proposed a different construction (“the database of individual land parcels having been 1 According to the ’957 patent, the Federal Information Processing Standards (“FIPS”) number “is used nationally to numerically identify specific county jurisdictions.” Ex. 1001, 7:27–30. 9 transformed by a set of one or more automated and/or semiautomated processes applied to data and data updates supplied by sponsoring jurisdictions using a set of rules or procedures”) for nearly the identical phrase (“multiple jurisdictional databases which have been normalized to a common data protocol”). Prelim. Resp. 15–17. We did not adopt Patent Owner’s proposed construction in our Decision to Institute, and we do not adopt its revised (and lengthier) construction in this Final Written Decision, for the reasons argued by Petitioner in its Reply (Reply 2–5) and also because the Patent Owner’s prolix proposed construction does not add clarity to the term. We decline to provide an express construction for this term or for any other terms in the claims other than discussed above.” slip op. at 9

  • Skill levelSkill level board ownOther

    “C. Level of Ordinary Skill in the Art Petitioner’s proposal for the level of ordinary skill in the art is “at least a bachelors degree in geographic information science, survey engineering, geomatics, or similar education, and two years of experience in a relevant field (e.g., land or geographic information science), or six years of experience in the relevant field.” Ex. 1006 (Declaration of Michael Goodchild), ¶ 11. Patent Owner has proposed that one of ordinary skill in the art would possess a “a Bachelor’s degree or higher in, GIS engineering with at least 5 years of academic or industry experience in GIS database design.” Ex. 2004 (Declaration of William Huxhold), ¶ 13. We determine that an express definition of the level of ordinary skill is not required. The level of ordinary skill in the art can be reflected in the cited prior art references. See Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001) (“[T]he absence of specific findings on the level of skill in the art does not give rise to reversible error where the prior art itself reflects an appropriate level and a need for testimony is not shown.”) (internal quotations omitted); In re GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995). Therefore, we find the level of ordinary skill in the art to be reflected in the cited references.” slip op. at 11

  • Obviousness (§103) › Graham factors (scope of art, differences, level of skill)UnpatentableUnpatentable

    “universal spatial protocol using SHP files (shapefiles) (Ex. 1001, 7:31–41), and Harder’s description of how its system’s datasets are “stored in the industry-standard shapefile (.shp) format” and how the system “converts the data into shapefiles.” Pet. Reply 9–11; Ex. 1003, 24, 106. Petitioner also notes that Patent Owner’s declarant acknowledged that assembling databases according to a standard protocol was in the prior art. Pet. Reply 11; Ex. 1034, 29:15–32:17, 32:18–40:22. We agree with Petitioner and find that Harder teaches or suggests databases that have been normalized to a common data protocol. Second, Patent Owner argues about the lack of disclosure of multiple jurisdictional databases. PO Resp. 28–29. Petitioner contends multiple jurisdictional databases are taught by both Harder and Longley, which explicitly discloses a “STATES table” that is a multi-state database. Pet. Reply 13; Ex. 1015, 229, Fig. 11.2. We agree with Petitioner and find that Harder and Longley teach or suggest multiple jurisdictional databases.” slip op. at 17

  Patent outcomesUS 7,092,957 unpatentable
  Claim construction§ 103 obviousnesscites KSR · Graham
  Patents in suitUS 7,092,957
• Smart Modular Technologies Inc. v. Netlist, Inc.No claims unpatentable
  PTAB · Mar 9, 2016 · IPR2014-01372 · APJ Linda M Gaudette · IPR · Final written decision

  The Board held claims 1–4, 14–20, 27, and 29 not unpatentable because Averbuj did not disclose a control module configured to generate the claimed address signals.

  RulingsFinal written decision

  • Skill levelSkill level petitioner adoptedDecided for petitioner

    “Based on a comparison of Dr. Bagherzadeh’s and Dr. Sechen’s declarations (Exs. 1009, 2019), we find Dr. Bagherzadeh has a broader range of educational and work experience, and, therefore, accord greater weight to his opinion as to the level of ordinary skill in the art. Dr. Bagherzadeh’s opinion is consistent with our finding as to the level of ordinary skill in the art in our Final Written Decision in IPR-970. We, therefore, adopt our finding in IPR-970 as to the level of ordinary skill in the art: [A] person of ordinary skill in the art at the time of the ’434 patent would have a Bachelor’s degree in electrical engineering, computer engineering, or in a related field and at least one year of work experience relating to memory systems, and would be familiar with the design of memory devices, memory modules, and BIST. IPR-970 FWD, 10–11 (noting that our finding was “based on our review of the ’434 patent and the types of problems and solutions described in the ’434 patent and cited prior art”).” slip op. at 10

  • Expert testimonyPetitioner expert discountedDecided for patent owner

    “We are not persuaded by Dr. Bagherzadeh’s testimony because it is devoid of specific facts and analysis as to what led him to conclude that a person of ordinary skill in the art would interpret the claim term “generate” in the manner Petitioner proposes. See id. Dr. Bagherzadeh does not explain how the IEEE definition supports an interpretation of generate as “cause or initiate transmission,” terms that do not appear in the IEEE definition. See id. Nor does Dr. Bagherzadeh identify other extrinsic evidence which he believes to be consistent with an interpretation of “generate” as meaning “cause or initiate transmission.” See id. Likewise, Dr. Bagherzadeh has not explained why he believes the ’434 patent “describe[s] generating as initiating or transmitting” (Ex. 1009 ¶ 28), as these terms do not appear in the cited portions of the ’434 patent. See Ex. 1008, 6:3–5, 10:67–11:2, 6:14–17. Accordingly, Dr. Bagherzadeh’s testimony does not persuade us to accept Petitioner’s interpretation of “generate” as meaning “cause.”” slip op. at 15

  • Claim Construction › Intrinsic evidence (Phillips canons) › Plain and ordinary meaning to a POSITATerm construed patent owner constructionDecided for patent owner

    “supports a finding that a customary meaning of “generate” to one of ordinary skill in the art is “cause.”1 We, therefore, determine the broadest reasonable 1 Petitioner relies on Webster’s II, for a definition of “cause.” See Reply 4, 6–8 (citing Ex. 1032, 3). Having determined the broadest reasonable interpretation of “generate” does not encompass “cause,” we do not find this evidence relevant to our claim construction analysis. construction of “generate” is “produce” for the reasons stated above and in our Final Written Decision in IPR-970. We adopt and incorporate by reference our analysis and construction of the term “generate” in our Final Written Decision in IPR-970 (IPR-970 FWD, 24–33).” slip op. at 16

  • Novelty / Anticipation (§102) › Anticipation standard (single reference, every element)Not shown unpatentableNot shown unpatentable

    “Moreover, the evidence in this proceeding fails to support a finding that Averbuj’s BIST controller 4 is configured to generate address signals for testing the memory devices in the manner claimed. In Averbuj, the algorithms (i.e., CMD_DATA containing OP CODE such as SET ADDRESS (see Ex. 1011, 4:4–12, 5:19–21, Table 1)) communicated to sequencers 8 are either received by user interface 22 via external input (id. at 5:41–43) or generated by another component (i.e., a component that is not part of BIST controller 4 circuitry) and stored in algorithm memory 20 (see Ex. 2012, 30:23–24, 41:1–4, 54:21–22, 55:6–25, 55:20–56:9 (wherein Dr. Bagherzadeh testifies that OP CODE residing in the algorithm memory of BIST controller 4 are generated by hand or by a tool, e.g., a compiler, and that “99 percent of the designs or chips do not have a compiler on-board”)). Multiplexer 24 selects one of the algorithms (i.e., CMD_DATA) and BIST controller 4 provides to sequencers 8 the same CMD_DATA (e.g., address signals) without transformation or modification. See Ex. 1011, 4:4–12, 5:16–21; Ex. 2012, 54:8–13 (“Averbuj Figure 2, without consideration of any other disclosure in Averbuj, illustrates that a multiplexer selects an input from the algorithm memory and the output [] reflect[s] what’s in the input, based on the selection.”). Based on our interpretation of the terms “configured to” and “generate,” as discussed above, the claim recitation “a control module configured to generate address . . . signals for testing the memory devices” (claims 1, 20, and 29) does not read on Averbuj’s BIST controller 4, because the SET ADDRESS signal output by BIST controller 4 is produced by a component external to BIST controller 4, and merely selected by multiplexer 24 and provided to sequencers 8 without transformation or modification by BIST controller 4. In sum, after considering the parties’ arguments and evidence, we determine Petitioner has not shown, by a preponderance of the evidence, that Averbuj discloses “a control module configured to generate address . . . signals for testing the memory devices” as recited in independent claims 1, 20, and 29. Petitioner does not correct this deficiency in its challenges as to dependent claims 2–4, 14–19, and 27. See Pet. 32–39; 35 U.S.C. § 112, ¶ 4 (“A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.”). Because Petitioner has not identified in Averbuj a teaching of each and every limitation recited in claims 1–4, 14–20, 27, and 29, Petitioner has not met its burden to show these claims are unpatentable under 35 U.S.C. § 102(b) as anticipated by Averbuj.” slip op. at 30

  Patent outcomesUS 8,001,434 not shown unpatentable
  Claim construction§ 102 anticipation
  Patents in suitUS 8,001,434
• Sure-Fire Electrical Corporation v. Yongjiang Yin And Shenzhen El Lighting Co. Ltd.All claims unpatentable
  PTAB · Feb 22, 2016 · IPR2014-01448 · APJ Debra K Stephens · IPR · Final written decision

  Claims 1 and 7 are unpatentable as obvious over He and Korodi; the Board did not reach the Gustafsson and He ground.

  RulingsFinal written decision

  • Claim Construction › Intrinsic evidence (Phillips canons) › Plain and ordinary meaning to a POSITAPlain and ordinary meaningDecided for petitioner

    “its claims, but instead, recited only “emits.” Patent Owner has not proffered any evidence or argument as to why “emits and dies” used in the ’279 Patent Specification, would have been abbreviated to “emits” in recitation of the claims. Nor is the term “emits” defined explicitly in the ’279 Patent Specification. Thus, we begin with the assumption that the term “emits” does not include “and dies,” as that comports with the plain and ordinary meaning of the word “emits” Thus, taking the plain and ordinary meaning at the time of the invention, we interpret “emits light in sequence” as “throws off or gives off or out light in a continuous or connected series” and interpret “emits in sequence” as “throws off or gives off or out, in a continuous or connected series” (see e.g., Merriam-Webster’s Collegiate Dictionary 377, 1065 (10th ed. 2000)). Patent Owner has not proffered sufficient evidence or argument that “emits light in sequence” and “emits in sequence” should be read more narrowly than the plain and ordinary meaning as suggested by Patent Owner. Specifically, Patent Owner’s assertion that the Specification supports the proposed interpretation of “emits light in sequence” as “emits and dies light in sequence” is misplaced. The Specification of the ’279 Patent does not explicitly define “emits light in sequence” as “emits and dies light in sequence.” Nor is any explicit definition provided for “emits light in sequence” or “emits in sequence.” Patent Owner would have us import limitations disclosed in several of the embodiments, including Embodiment 1, to interpret “emits” as “emits and dies light in sequence” or “emits and” slip op. at 9

  • Claim Construction › Intrinsic evidence (Phillips canons) › Prosecution history disclaimer / disavowalDisclaimer not foundDecided for petitioner

    “Patent Owner additionally asserts “Patent Owner specifically disclaimed emission of light over the full length of the cable, but rather limited the patent to segment by segment illumination along the length of the cable,” thereby limiting the phrase “emits light in sequence” (PO Resp. 43). Patent Owner identified pages 9–10 of the Response to Office Action filed September 18, 2009 (Ex. 1002, 25–26), as providing this disclaimer (PO Resp. 48–49). However, we agree with Petitioner that the statements in the Response to Office Action do not disclaim subject matter, nor do these statements provide an explicit definition of “emits,” “emits light in sequence, and “emits in sequence.” Indeed, the discussion, limited to claim 7, discusses the object of the invention and distinguishes the invention as recited in claim 7 over the cited prior art, Baumberg et al. (US 5,869,930) (Resp. to OA 9–10). This discussion does not qualify as “clear and unmistakable” disavowing statements as required to meet the “demanding standard for finding a disclaimer.” Avid Tech., Inc. v. Harmonic, Inc., No. 2015-1246, 2016 WL 363410, at *4 (Fed. Cir. Jan. 29, 2016). We, therefore, determine the term “emits light in sequence” and “emits in sequence” used in the claims, should not be interpreted as “emits and dies light of each electroluminescent cored bar or cord in succession, one after the other,” but instead, should be interpreted giving the terms their ordinary and customary meaning as understood by an ordinarily skilled artisan at the time of the invention, in light of the Specification.” slip op. at 10

  • Obviousness (§103) › Analogous artAnalogous artDecided for petitioner

    “(PO Resp. 37–40). A reference qualifies as prior art for an obviousness determination under § 103 only when it is analogous to the claimed invention. Innovention Toys, LLC, v. MGA Entm’t, Inc., 637 F.3d 1314, 1322 (Fed. Cir. 2011); In re Bigio, 381 F.3d 1320, 1325 (Fed. Cir. 2004); In re Clay, 966 F.2d 656, 658 (Fed. Cir. 1992). “Two separate tests define the scope of analogous prior art: (1) whether the art is from the same field of endeavor, regardless of the problem addressed and, (2) if the reference is not within the field of the inventor’s endeavor, whether the reference still is reasonably pertinent to the particular problem with which the inventor is involved.” Bigio, 381 F.3d at 1325 (citations omitted).” slip op. at 18

  • Obviousness (§103) › Motivation to combine / reasonable expectation of successMotivation foundDecided for petitioner

    “Nonetheless, we find Petitioner has articulated reasoning with a rational underpinning as to why an ordinarily skilled artisan would have been motivated to combine the teachings (Pet. 34–36; Ex. 1008 ¶¶ 98–104). Specifically, Petitioner contends an ordinarily skilled artisan would have been motivated to combine the teachings of He and Korodi because “such a modification is both a predictable variation and an incremental improvement” (Pet. 35). According to Petitioner, an ordinarily skilled artisan would have found it obvious and “straight-forward” to replace the aluminum core wire in He with a power cord to create an improved illuminated cable using electroluminescent wires that light in sequence (id. at 36). Petitioner further asserts combining the teachings would “involve the merger of familiar elements according to their established functions, known methods, and predictable results” (id.). We agree with the Petitioner that an ordinarily skilled artisan would have been motivated to replace the core wire at the center of He’s cable with a power cord as taught by Korodi to create an improved illuminated cable. We find the combination of He and Korodi unites old elements with no change in their respective functions. Indeed, we agree that combining the teachings would be a merger of familiar elements, Korodi’s power cord and He’s electroluminescent cable, that perform their ordinary functions to predictably result in the recited cable which includes a main power cord and a plurality of electroluminescent cords which emit light in sequence when the main cord and the driver are live. To be nonobvious, an improvement must be “more than the predictable use of prior art elements according to their established functions.” KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 417 (2007). Additionally, as further support, we credit Petitioner’s Declarant’s, Dr. Mark Horenstein’s, testimony that replacing the aluminum core wire in He for the power cord in Korodi would have been a merger of familiar elements according to their established functions, known methods, and predictable results that an ordinarily skilled artisan would have found obvious (Ex. 1008 ¶¶ 99, 102, 103).” slip op. at 20

  Patent outcomesUS 7,671,279 unpatentable
  Claim construction§ 103 obviousnesscites KSR
  Patents in suitUS 7,671,279
• Great West Casualty Company / Bitco General Insurance Corporation et al. v. Intellectual Ventures II LLCInstitution denied
  PTAB · Feb 9, 2016 · CBM2015-00171 · APJ Michael W Kim · CBM · Institution

  The Board denied institution because Petitioner did not show that any existing claim qualified as a covered business method patent under AIA § 18(d)(1).

  RulingsInstitution decision

  • PTAB / AIA Trials › Institution threshold (reasonable likelihood / more likely than not)Institution denied meritsInstitution denied

    “that the patent for which review is sought is a covered business method patent.” The AIA defines “covered business method patent” as “a patent that claims a method or corresponding apparatus for performing data processing or other operations used in the practice, administration, or management of a financial product or service, except that the term does not include patents for technological inventions.” AIA § 18(d)(1); see 37 C.F.R. § 42.301(a).” slip op. at 6

  • Adverse judgmentAdverse judgmentOther

    “disclaimer under 37 C.F.R. § 1.321(a) of claims 1–10. Prelim. Resp. 13 (citing Ex. 2002). Thus, the question is whether we should consider now-statutorily disclaimed claims 1–10 in determining whether or not the ’177 patent is a covered business method patent for the purposes of instituting a covered business method patent review. We determine that we should not. 37 C.F.R. § 1.321(a) is the rule promulgated by the Office for creating a procedure for a patentee to avail itself of the provisions of 35 U.S.C. § 253. See Manual of Patent Examining Procedure § 1490. Our reviewing court has held that a patent with a statutory disclaimer is to be treated as though the disclaimed claims never existed. See Guinn v. Kopf, 96 F.3d 1419, 1422 (Fed. Cir. 1996) (“A statutory disclaimer under 35 U.S.C. § 253 has the effect of canceling the claims from the patent and the patent is viewed as though the disclaimed claims had never existed in the patent.”). Accordingly, for the purposes of whether or not to institute a covered business method patent review, we treat claims 1–10 as never having existed. See Google Inc. v. SimpleAir, Inc., CBM2015-00019 slip op. at 14– 15 (PTAB May 19, 2014) (Paper 11); but see J.P. Morgan Chase v. Intellectual Ventures, Case CBM2014-00157 slip op. at 12–15 (PTAB Jan. 12, 2016) (Paper 40) (although the panel states that “petitioner’s standing to file a petition for covered business method patent review is evaluated based on the time the petition was filed,” in this proceeding, Patent Owner” slip op. at 7

  • Claim Construction › Threshold & procedure › Whether a term needs construction (O2 Micro)Term construed petitioner constructionDecided for petitioner

    “unexpired patent are interpreted according to their broadest reasonable construction in light of the specification of the patent in which they appear. 37 C.F.R. § 42.300(b); Versata Dev. Grp., Inc. v. SAP Am., Inc., 793 F.3d 1306, 1328 (2015) (affirming use of the broadest reasonable construction standard in a covered business method patent review). Under that standard, and absent any special definitions, we give claim terms their ordinary and customary meaning, as would be understood by one of ordinary skill in the art at the time of the invention. In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007).” slip op. at 5

  Claim construction
  Patents in suitUS 7,516,177
• Ericsson Inc. / Telefonaktiebolaget LM Ericsson v. Intellectual Ventures II LLCAll claims unpatentable
  PTAB · Jan 21, 2016 · IPR2014-01185 · APJ Peter P Chen · IPR · Final written decision

  Claims 1–10 and 17 are unpatentable: claims 1–3 and 5 as obvious over Schmidl and Arslan; claims 4 and 6–10 over those references and Kim; claim 17 over those references and Heiskala.

  RulingsFinal written decision

  • Claim Construction › Intrinsic evidence (Phillips canons) › Plain and ordinary meaning to a POSITATerm construed board ownDecided for petitioner

    “Our interpretation of the disputed term begins with the language of the claim. See Microsoft Corp. v. Proxyconn Inc., 789 F.3d 1292, 1299 (Fed. Cir. 2015). Claim 1 recites that pilot symbols are inserted “into data blocks.” We construe claim 1’s plain language using the plural form of “data blocks” to mean that pilot symbols may be inserted not only within a single data block, as Patent Owner contends, but also between one data block and another data block, as Petitioner contends. Claims should also be read in light of the specification and teachings in the underlying patent. Cuozzo, 793 F.3d at 1280; Microsoft, 789 F.3d at 11 1298. Here, the specification also uses the plural form of data blocks in explaining that “[t]ypically, pilot symbols may be inserted at any point in the data blocks.” Ex. 1001, 16:55–56, 7:28–29. There is no language in the specification disclaiming the insertion of pilot symbols between data blocks. We are persuaded that based on the claim’s usage of the plural “data blocks,” which is supported by the description in the specification, the broadest reasonable construction is “pilot/training symbol inserter configured to insert pilot symbols within, or between, one or more data blocks,” and accordingly, does not exclude the insertion of pilot symbols between two data blocks that are in a group of data blocks.” slip op. at 11

  • Skill levelSkill level board ownOther

    “We determine that an express definition of the level of ordinary skill is not required. The level of ordinary skill in the art can be reflected in the 13 cited prior art references. See Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001) (“[T]he absence of specific findings on the level of skill in the art does not give rise to reversible error where the prior art itself reflects an appropriate level and a need for testimony is not shown.”) (internal quotations omitted); In re GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995). Therefore, we find the level of ordinary skill in the art to be reflected in the cited references.” slip op. at 13

  • Obviousness (§103) › Motivation to combine / reasonable expectation of successMotivation foundUnpatentable

    “that “both Schmidl and Arslan are directed at improving synchronization between a wireless transmitter and a wireless receiver, and disclose frame structures including information for the same.” Pet. 16. In particular, Schmidl discloses an encoder that inserts training symbols in the frequency domain, to form training symbols in the time domain. Pet. Reply 13, 17 (citing Ex. 1036 ¶ 21); see Ex. 1002, 2:7–17. Arslan discloses a frame structure in the time domain containing pilot symbols interspersed among data symbols. Pet. Reply 16–17 (citing Ex. 1036 ¶¶ 20, 22). Petitioner further states: [I]t would have been obvious to use pilot symbols as separate time domain symbols for tracking time variations to calibrate or synchronize the receiver to the transmitter by using time-domain pilot symbols in Schmidl’s system. . . [citing to Supplemental Declaration of Dr. Zygmunt Haas ¶ 22.] As discussed above, Schmidl discloses inserting symbols in the frequency domain for an OFDM system, for calibration and synchronization. See id. It would have been obvious to create those time-domain pilot symbols in the same manner as the time-domain training symbols are created in Schmidl’s encoder – that is, by inserting blocks of known pilot symbols in the frequency domain that would result in time-domain pilot symbols. See id. It would be obvious to a POSA that the same circuitry in Schmidl’s encoder 14 used to insert training symbols would be used to insert pilot symbols, resulting in the claimed “pilot/training symbol inserter configured to insert pilot symbols into data blocks.” See id. Pet. Reply 17–18; see Pet. 16, 29–30.” slip op. at 22

  Patent outcomesUS 7,269,127 unpatentable
  Claim construction§ 103 obviousnesscites KSR
  Patents in suitUS 7,269,127
• Atoptech, Inc. v. Synopsys, Inc.All claims unpatentable
  PTAB · Jan 19, 2016 · IPR2014-01159 · APJ Peter P Chen · IPR · Final written decision

  Claims 5, 23, 24, and 27 are unpatentable as obvious; claim 31 was not shown anticipated, and claim 26 was not shown obvious.

  RulingsFinal written decision

  • Prior constructionPrior construction adoptedDecided for petitioner

    “In our Decision to Institute, we construed “place and route unit (PRU).” We determined that the broadest reasonable interpretation of that term is, “a section of the IC design created to represent the physical partitioning of the IC design.” Dec. to Inst., 10. Neither party disputes that construction in their post-institution filings.” slip op. at 10

  • Claim Construction › Intrinsic evidence (Phillips canons) › Lexicography (patentee as own lexicographer)Term construed patent owner constructionDecided for patent owner

    “in the underlying patent. In re Cuozzo, 793 F.3d at 1280; Microsoft Corporation v. Proxyconn Inc., 789 F.3d at 1298. Here, the specification expressly defines atomic blocks: Defining Atomic ("A") blocks (sometimes called units) – “A” blocks are the netlist blocks that will be physically partitioned to create place and route units (PRUs). "A" blocks may contain only standard cells or they may contain additional levels of hierarchy. For the purpose of partitioning the circuit design into PRUs, the "A" blocks are indivisible. Ex. 1001, 4:8–12. Consistent with the patentee’s express definition of atomic block, we determine the broadest reasonable interpretation of atomic block to be, “a netlist block that is indivisible for the purpose of physically partitioning the circuit design into place and route units (PRUs).”” slip op. at 11

  • Skill levelSkill level board ownDecided for petitioner

    “C. Level of Ordinary Skill in the Art Petitioner has not proposed a level of ordinary skill in the art. Patent Owner proposes that one of ordinary skill in the art would possess a “Bachelor of Science degree in Electrical Engineering, Computer Engineering, or a closely related field,” as well as “a minimum of one to two years of professional experience in the engineering development of integrated circuit technology.” Ex. 2004 (Declaration of Daniel Foty, Ph.D.), ¶ 15. At the oral hearing, Petitioner stated it had no dispute with Patent Owner’s proposal. Tr. 16:21–17:2. We determine that an express definition of the level of ordinary skill is not required. The level of ordinary skill in the art can be reflected in the cited prior art references. See Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001) (“the absence of specific findings on the level of skill in the art does not give rise to reversible error where the prior art itself reflects an appropriate level and a need for testimony is not shown.”) (internal quotations omitted); In re GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995). Therefore, we find the level of ordinary skill in the art to be reflected in the cited references.” slip op. at 12

  • Expert testimonyPetitioner expert creditedDecided for petitioner

    “directed at efficient circuit design involving large and complex circuits, and determine that, as set forth in the VLSI textbook, FPGA is indeed a type of layout for physical design. We also credit the testimony of Dr. Ghiasi, who opines that: While Fields presents this logical approach to IC floorplanning in the context of FPGA design, one of ordinary skill as of September 2000 would have understood that the general teachings of Fields could be applied to the design of an ASIC chip as well as an FPGA chip and would have been motivated to apply the teaching of Fields to solve the problem of very large IC chip design. . . . One of ordinary skill in the field of EDA design would be familiar with IC design for both ASIC and FPGA formats and would rely on teachings in the context of FPGA chip design, especially in the front end of an EDA design flow, through floorplanning and partitioning of the physical design in addressing problems in ASIC chip design, and vice versa. Ex. 1009 ¶¶ 72–73. Even assuming arguendo the Board were to accept Patent Owner’s assertion that design of an FPGA is “completely different” from design of an integrated circuit, the Supreme Court’s decision in KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007) stated, “[w]hen a work is available in one field of endeavor, design incentives and other market forces can prompt variations of it, either in the same field or a different one.” Thus, under KSR, such purportedly “different” teachings of Fields about FPGA design could be applicable to the physical design of an integrated circuit as described in the ’967 patent and in Su. We are persuaded by Petitioner’s evidence, including the VLSI textbook and the Ghiasi declaration, and find that one of ordinary skill in the art would have understood the applicability of Fields’ FPGA teachings to physical design of an integrated circuit as recited in claim 1 of the ’967 patent.” slip op. at 25

  Patent outcomesUS 6,567,967 unpatentable
  Claim construction§ 102 anticipation§ 103 obviousnesscites KSR
  Patents in suitUS 6,567,967
• Atoptech, Inc. v. Synopsys, Inc.All claims unpatentable
  PTAB · Jan 19, 2016 · IPR2014-01145 · APJ Trenton A Ward · IPR · Final written decision

  Claims 1–4 and 7–11 are unpatentable as obvious over Belkhale alone and over Belkhale in combination with Tom.

  RulingsFinal written decision

  • Skill levelSkill level patent owner adoptedDecided for patent owner

    “view of the ’127 patent, a person of ordinary skill in the art would have a minimum of a Bachelor of Science degree in Electrical Engineering, Computer Engineering, or a closely related field and would have a minimum of one to two years of professional experience in the development and analysis of digital electronic circuits. Ex. 2004, Declaration of Dr. Martin G. Walker ¶ 22. Petitioner does not disagree with Dr. Walker’s opinion as to the proper level of ordinary skill in the art. Pet. Reply 17. Based on our review of the ’127 patent and the testimony of Patent Owner’s Declarant, we adopt Patent Owner’s definition of a person of ordinary skill in the art at the time of the claimed invention. Furthermore, as noted in the Decision on Institution, the applied prior art also reflects the appropriate level of skill at the time of the claimed invention. See Dec. on Inst. 23 (citing Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001) (“the absence of specific findings on the level of skill in the art does not give rise to reversible error where the prior art itself reflects an appropriate level and a need for testimony is not shown.”) (internal quotations omitted); In re GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995)).” slip op. at 5

  • Claim Construction › Intrinsic evidence (Phillips canons) › Plain and ordinary meaning to a POSITATerm construed petitioner constructionDecided for petitioner

    “circuit under non-default timing constraints known as exceptions.” Ex. 1001, 1:8–11; see id. at Title, Abstract. The Specification adds “[e]xceptions are specified by the circuit designer as individual syntactic units called ‘exception statements’ which are comprised of a ‘timing alteration’ and a ‘path specification.’” Ex. 1001, 1:58–61. The timing alteration instructs the timing analyzer how to alter the default timing constraints for paths through the circuit to be analyzed which satisfy the path specification. Id. at 1:61–63. The Specification further states, “[t]he path specification consists of one or more ‘path specifiers,’ with each path specifier taking an ‘argument.’ In order for a path specification to be satisfied, each argument of each of its path specifiers must be satisfied.” Id. at 1:64–67. In view of the foregoing, we maintain the construction provided in the Decision on Institution (Dec. on Inst. 7) and construe the term “exception” as “non-default timing constraints.”” slip op. at 8

  • Claim Construction › Threshold & procedure › Whether a term needs construction (O2 Micro)Term construed board ownDecided for patent owner

    “Petitioner counters that Patent Owner’s arguments fail to provide any evidence that a “set” must include more than a single data item. Pet. Reply. 3. Petitioner argues that both the ’127 patent and Belkhale refer to a “null set,” which is a set having no data items. Id. (citing Ex. 1001, Fig. 9A, 9E; Ex. 1005 at 737). We agree with Petitioner that the term “table” does not require multiple data items and, likewise, that the term “timing table” does not require multiple delay values. Although the Specification discloses an exemplary “RF timing table” as having four RF values (Ex. 1001, 9:54–57), the claim language is broader and not restricted to a specific type of table or number of data items in the table. To require otherwise would improperly import a limitation from the Specification into the claim. See, e.g., SuperGuide Corp. v. DirecTV Enters., Inc., 358 F.3d 870, 875 (Fed. Cir. 2004) (“Though understanding the claim language may be aided by the explanations contained in the written description, it is important not to import into a claim limitations that are not a part of the claim.”). In view of the foregoing, we maintain the construction provided in the Decision on Institution (Dec. on Inst. 7) and determine the broadest reasonable interpretation of “timing table” is a “table having a timing value.”” slip op. at 9

  • Obviousness (§103) › Graham factors (scope of art, differences, level of skill)UnpatentableUnpatentable

    “We are persuaded that Belkhale’s false paths and false sub graphs teach or suggest the claimed “exception.” As Petitioner observes, Belkhale describes false paths as paths that are not logically realizable and must be detected and eliminated from the timing analysis. Pet. 13 (citing Ex. 1005, 736). Likewise, Belkhale explains that removing an entire false sub graph from timing consideration is advantageous because multiple paths may be simultaneously removed from consideration. See Pet. 13–14 (citing Ex. 1005, 736; Ex. 1007 ¶ 78). Accordingly, we are persuaded by Petitioner’s argument that Belkhale’s false path and false sub graph are each a non-default timing constraint (i.e., an exception) because they represent circuit pathways that are not logically realizable and must be eliminated from the timing analysis. Id. Second, we also are persuaded Petitioner has established sufficiently how Belkhale’s ordered pair vertices or Algorithm 1 disclose “marking certain points in a circuit description according to their being referenced by,” recited in claim 1, a false path or false sub graph. As Petitioner points out, Belkhale defines false paths in a multiplexer circuit with ordered pair vertices. Additionally, Petitioner separately equates Belkhale’s use of “three separate data structures” BG(v), EG(v), and IN(e) to associate points in the circuit description with the false sub graph. Pet. 21–22; see Pet. 16–18 (explaining Algorithm 1 in operation). We understand Petitioner’s latter argument to be that Belkhale’s timing graph “G” discloses a circuit description, the false sub graphs disclose exceptions, and the three data sets define vertices and edges according to a relationship to the false sub graphs.” slip op. at 13

  Patent outcomesUS 6,237,127 unpatentable
  Claim construction§ 103 obviousnesscites KSR · Graham
  Patents in suitUS 6,237,127
• Atoptech, Inc. v. Synopsys, Inc.All claims unpatentable
  PTAB · Jan 19, 2016 · IPR2014-01150 · APJ Peter P Chen · IPR · Final written decision

  Claims 1, 4, 8, 9, 12, 16, 19–22 are unpatentable as obvious over Fields and Su; claims 32–36 are unpatentable as anticipated by Su.

  RulingsFinal written decision

  • Skill levelSkill level board ownDecided for patent owner

    “Owner proposes that one of ordinary skill in the art would possess a “Bachelor of Science degree in Electrical Engineering, Computer Engineering, or a closely related field,” as well as “a minimum of one to two years of professional experience in the engineering development of integrated circuit technology.” Ex. 2004 (Declaration of Daniel Foty, Ph.D.), ¶ 15. At the oral hearing, Petitioner stated it had no dispute with Patent Owner’s proposal. Tr. 16:21–17:2. We determine that an express definition of the level of ordinary skill is not required. The level of ordinary skill in the art can be reflected in the cited prior art references. See Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001) (“the absence of specific findings on the level of skill in the art does not give rise to reversible error where the prior art itself reflects an appropriate level and a need for testimony is not shown.”) (internal quotations omitted); In re GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995). Therefore, we find the level of ordinary skill in the art to be reflected in the cited references.” slip op. at 12

  • Claim Construction › Intrinsic evidence (Phillips canons) › Lexicography (patentee as own lexicographer)Term construed patent owner constructionDecided for patent owner

    “in the underlying patent. In re Cuozzo, 793 F.3d at 1280; Microsoft Corporation v. Proxyconn Inc., 789 F.3d at 1298. Here, the specification expressly defines atomic blocks: Defining Atomic ("A") blocks (sometimes called units) – “A” blocks are the netlist blocks that will be physically partitioned to create place and route units (PRUs). "A" blocks may contain only standard cells or they may contain additional levels of hierarchy. For the purpose of partitioning the circuit design into PRUs, the "A" blocks are indivisible. Ex. 1001, 4:8–12. Consistent with the patentee’s express definition of atomic block, we determine the broadest reasonable interpretation of atomic block to be, “a netlist block that is indivisible for the purpose of physically partitioning the circuit design into place and route units (PRUs).”” slip op. at 10

  • Obviousness (§103) › Analogous artAnalogous artDecided for petitioner

    “We agree with Petitioner that the ’967 patent, Fields, and Su are all directed at efficient circuit design involving large and complex circuits, and determine that, as set forth in the VLSI textbook, FPGA is indeed a type of layout for physical design. We also credit the testimony of Dr. Ghiasi, who opines that: While Fields presents this logical approach to IC floorplanning in the context of FPGA design, one of ordinary skill as of September 2000 would have understood that the general teachings of Fields could be applied to the design of an ASIC chip as well as an FPGA chip and would have been motivated to apply the teaching of Fields to solve the problem of very large IC chip design. . . . One of ordinary skill in the field of EDA design would be familiar with IC design for both ASIC and FPGA formats and would rely on teachings in the context of FPGA chip design, especially in the front end of an EDA design flow, through floorplanning and partitioning of the physical design in addressing problems in ASIC chip design, and vice versa. Ex. 1009 ¶¶ 72–73. Even assuming arguendo the Board were to accept Patent Owner’s assertion that design of an FPGA is “completely different” from design of an integrated circuit, the Supreme Court’s decision in KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007) stated, “[w]hen a work is available in one field of endeavor, design incentives and other market forces can prompt variations of it, either in the same field or a different one.” Thus, under KSR, such purportedly “different” teachings of Fields about FPGA design could be applicable to the physical design of an integrated circuit as described in the ’967 patent and in Su. We are persuaded by Petitioner’s evidence, including the VLSI textbook and the Ghiasi declaration, and find that one of ordinary skill in the art would have understood the applicability of Fields’ FPGA teachings to physical design of an integrated circuit as recited in claim 1 of the ’967 patent.” slip op. at 19

  • Obviousness (§103) › Motivation to combine / reasonable expectation of successMotivation foundDecided for petitioner

    “directed at efficient circuit design involving large and complex circuits, and determine that, as set forth in the VLSI textbook, FPGA is indeed a type of layout for physical design. We also credit the testimony of Dr. Ghiasi, who opines that: While Fields presents this logical approach to IC floorplanning in the context of FPGA design, one of ordinary skill as of September 2000 would have understood that the general teachings of Fields could be applied to the design of an ASIC chip as well as an FPGA chip and would have been motivated to apply the teaching of Fields to solve the problem of very large IC chip design. . . . One of ordinary skill in the field of EDA design would be familiar with IC design for both ASIC and FPGA formats and would rely on teachings in the context of FPGA chip design, especially in the front end of an EDA design flow, through floorplanning and partitioning of the physical design in addressing problems in ASIC chip design, and vice versa. Ex. 1009 ¶¶ 72–73. Even assuming arguendo the Board were to accept Patent Owner’s assertion that design of an FPGA is “completely different” from design of an integrated circuit, the Supreme Court’s decision in KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007) stated, “[w]hen a work is available in one field of endeavor, design incentives and other market forces can prompt variations of it, either in the same field or a different one.” Thus, under KSR, such purportedly “different” teachings of Fields about FPGA design could be applicable to the physical design of an integrated circuit as described in the ’967 patent and in Su. We are persuaded by Petitioner’s evidence, including the VLSI textbook and the Ghiasi declaration, and find that one of ordinary skill in the art would have understood the applicability of Fields’ FPGA teachings to physical design of an integrated circuit as recited in claim 1 of the ’967 patent.” slip op. at 19

  Patent outcomesUS 6,567,967 unpatentable
  Claim construction§ 102 anticipation§ 103 obviousnesscites KSR
  Patents in suitUS 6,567,967

Holdings, summaries, rulings, issues, outcomes, winners and claim constructions shown for a decision were generated by a large language model reading the opinion. They are a guide to the decision, not the decision. Confirm every one against the court's own text before relying on it. Outcomes read from the patent owner’s side. Party names are extracted from the decision and are missing on about 900 short Director denials and scans, which carry the trial number instead.