• Apple Inc. v. Corephotonics Ltd.All claims unpatentable
  PTAB · Dec 6, 2021 · IPR2020-00897 · APJ Gregg I Anderson · IPR · Final written decision

  Claims 1–24 are unpatentable as obvious over Ogino Example 5 and Bareau; claims 1–3 and 5–8 are also unpatentable over Ogino Example 4 and Bareau.

  RulingsFinal written decision

  • Skill levelSkill level petitioner adoptedDecided for petitioner

    “had “(i) a bachelor’s degree in Physics, Optical Sciences, or equivalent training, as well as (ii) approximately three years of experience in designing multi-lens optical systems.” Pet. 7 (citing Ex. 1003, 1111). Petitioner further alleges a person of ordinary skill “would have known how to use lens design software such as Code V, Oslo, or Zemax, and would have taken a lens 9 The Leahy-Smith America Invents Act (AIA), Pub. L. No. 112-29, 125 Stat. 284, 285–88 (2011) revised 35 U.S.C. §§ 102 and 103, effective March 16, 2013. The ’277 patent has an effective filing date later than March 16, 2013 (see Section II.C, fn. 5). Thus, the grounds asserted are under the AIA version of 35 U.S.C. § 103. 10 Petitioner primarily relies on Examples 4 and 5, but also cites Example 6. See, e.g., Pet. 27. We consider all cited portions of Ogino. 11 Petitioner alternates its citations to the Sasián Declaration (Ex. 1003) between page numbers and paragraph numbers. Compare Pet. 7 (citing page) with Pet. 9 (citing paragraph). We refer to page numbers, which are used more often in the Petition, using paragraph cites when they are referenced. design course.” Id. (citing Ex. 1003 ¶ 19). Patent Owner “does not disagree” with Petitioner’s proposed description of a person of ordinary skill in the art. PO Resp. 12 (citing Ex. 2001 ¶ 20). On this record, and to the extent relevant to our findings, we adopt Petitioner’s proposal which is consistent with the prior art of record.” slip op. at 8

  • Prior constructionPrior construction adoptedDecided for petitioner

    “and “total track length” (“TTL”)12 in the final decisions in the ’1140 and ’1146 IPRs. Pet. 8; id. at fn. 2. Specifically, our analysis concluded “effective focal length” is “the focal length of a lens assembly.” ’1140 IPR, Paper 37, 10; ’1146 IPR, Paper 37, 8. We further concluded “total track 12 We also noted in the Institution Decision that Petitioner proposed a different construction of TTL in IPR2020-00877 (“’877 IPR”), which involves the same parties. Inst. Dec. 11. The parties were advised to “address during trial whether and why the construction of this term should differ.” Id. Neither party did so. length” is “the length of the optical axis spacing between the object-side surface of the first lens element and one of: an electronic sensor, a film sensor, and an image plane corresponding to either the electronic sensor or a film sensor.” ’1140 IPR, Paper 37, 10–18; ’1146 IPR, Paper 37, 8–14. The challenged patents in the ’1140 and ’1146 IPRs share common subject matter with the ’277 patent. See Section II.B above. Neither party disputes the constructions of EFL and TTL from the ’1140 or ’1146 IPRs as set forth above. Pet. 8; PO Resp. 13. There is no dispute as to the meaning of EFL or TFL. Accordingly, to the extent relevant and to complete the record, we maintain the above constructions of EFL and TTL for purposes of this Decision.” slip op. at 9

  • Claim Construction › Threshold & procedure › Whether a term needs construction (O2 Micro)No construction needed

    “2. Remaining claim terms In the Institution Decision, we determined no other claim term required construction. Inst. Dec. 10–11. Both parties agree that the remaining words of the claims do not require express construction and are given their ordinary and customary meaning as understood by a person of ordinary skill in the art. Pet. 8; PO Resp. 13.” slip op. at 10

  • Expert testimonyPetitioner expert creditedDecided for petitioner

    “We find that Dr. Sasián’s lens design software analysis using the Zemax software shows that L4 and L5 do not touch. See Reply 8–9 (citing Ex. 1037 ¶ 14 (Zemax ray analysis showing L4 and L5 do not touch)).29 Patent Owner disputes the design process used by Dr. Sasián but does not rebut the ray analysis and did not provide a response from Dr. Milster. See Sur-Reply 5–7. In making our finding, we credit Dr. Sasián’s opinion testimony as supported by his ray analysis. Regardless, as we have already found, manufacturing considerations such as touching lenses do not provide a reason not to combine Bureau with Ogino Example 4.” slip op. at 29

  Patent outcomesUS 10,324,277 unpatentable
  Claim construction§ 103 obviousnesscites Phillips · KSR · Graham
  Patents in suitUS 10,324,277
• Bright Data Ltd. v. Metacluster LT, UabInstitution denied
  PTAB · Dec 1, 2021 · IPR2021-00983 · APJ Debra K Stephens · IPR · Institution

  The Board denied institution because the petition did not show a reasonable likelihood of prevailing on any challenged claim under the asserted anticipation or obviousness grounds.

  RulingsInstitution decision

  • PTAB / AIA Trials › Institution threshold (reasonable likelihood / more likely than not)Institution denied meritsInstitution denied

    “(a) THRESHOLD.—The Director may not authorize an inter partes review to be instituted unless the Director determines that the information presented in the petition filed under section 311 and any response filed under section 313 shows that there is a reasonable likelihood that the petitioner would prevail with respect to at least 1 of the claims challenged in the petition” slip op. at 2

  • Skill levelSkill level board ownOther

    “Patent Owner does not contest Petitioner’s assertion (see generally Prelim. Resp.). The prior art itself demonstrates the level of ordinary skill in the art at the time of the invention (see Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001) (explaining that specific findings regarding ordinary skill level are not required “where the prior art itself reflects an appropriate level and a need for testimony is not shown”) (quoting Litton Indus. Prods., Inc. v. Solid State Sys. Corp., 755 F.2d 158, 163 (Fed. Cir. 1985))). in light of Petitioner’s definition of the level of ordinary skill in the art, we determine an ordinarily skilled artisan is: an individual who had (1) a bachelor’s degree or equivalent in the field of Electrical Engineering, Computer Engineering, or Computer Science, or in an equivalent field that includes network engineering as a topic of study (hereinafter, “technical study”), plus at least one year of industry technical experience in the computer network field, such as serving as an engineer for an Internet service provider performing network design, development, or configuration tasks, or as a software developer for network communications software or related utility software, or (2) three years of full-time technical experience in the field of electrical engineering, computer engineering, or computer science or in an equivalent field that includes network engineering or network communications software (hereinafter, “technical fields”), or (3) an equivalent combination of academic study in technical study and work experience in the technical fields.” slip op. at 9

  • Claim Construction › Intrinsic evidence (Phillips canons) › Lexicography (patentee as own lexicographer)Term construed patent owner constructionDecided for patent owner

    “Proxy Rotator’ as ‘a system coupled of separate components implementing a specific method and responsible for collecting statistical data, proxy control, rotation, maintenance, and reporting’” (Prelim. Resp. 15 (citing Ex. 1001, 5:4–7)). of separate components implementing a specific method and responsible for collecting statistical data, proxy control, rotation, maintenance, and reporting” (id. at 5:4–7). In accordance with the Specification’s “general terminology description,” we construe the term “Smart Proxy Rotator” as a system coupled of separate components implementing a specific method and responsible for collecting statistical data, proxy control, rotation, maintenance, and reporting.” slip op. at 11

  • Claim Construction › Intrinsic evidence (Phillips canons) › Plain and ordinary meaning to a POSITATerm construed board ownDecided for patent owner

    “construed as “‘the portion of all proxy requests received by the SPR during a time period that the SPR will refer to a particular proxy provider,’ which may be equal to the weight assigned to that particular proxy provider divided by the sum of weights assigned to all proxy providers during the same time period” (Prelim. Resp. 20 (citing Ex. 2003 ¶ 56)). Patent Owner’s definition requiring a “utilization threshold” to be a “portion of all proxy requests received by the SPR during a time period that the SPR will refer to a particular proxy provider” is too narrow. The ’948 Patent does not expressly define the term “utilization threshold,” and, instead, describes utilization thresholds using an example (id. at 8:1–8). The ’948 Patent states [o]ne of the usage examples can be the following: if one provider has a weight equal to 10, and the other provider has a weight equal to 20, the proxy rotator should use the second provider 66.6% of the time and the first provider 33.3% of the time, when no changes to the default providers’ weights have been introduced. These percentages are the utilization thresholds of each provider. threshold is a goal amount of use, not an actual amount of use. A utilization threshold may represent a desired maximum percentage (i.e., proportion), of proxy requests to be referred to a particular proxy provider. Based on the Specification’s use of a “utilization threshold,” we construe the term to mean “a maximum percentage of use assigned to a particular proxy provider that is equal to a weight for the particular proxy provider divided by the sum of respective weights assigned to all proxy providers during the same time period.”” slip op. at 14

  Claim construction§ 102 anticipation§ 103 obviousnesscites Phillips · KSR · Graham
  Patents in suitUS 10,601,948
• Samsung Electronics Co., Ltd. / Taiwan Semiconductor Manufacturing Co. Ltd. v. Arbor Global Strategies LLCAll claims unpatentable
  PTAB · Nov 24, 2021 · IPR2021-00391 · APJ Karl D Easthom · IPR · Final written decision

  Claims 1, 3, 5–9, 11, 13–17, 19–22, 25, 26, 28, and 29 are unpatentable as anticipated by Alexander or obvious over the stated prior-art combinations.

  RulingsFinal written decision

  • Skill levelSkill level petitioner adoptedDecided for petitioner

    “We adopt Petitioner’s proposed level of ordinary skill in the art as we did in the Institution Decision, which comports with the teachings of the ’035 patent and the asserted prior art. See Inst. Dec. 19. Patent Owner’s proposed level is slightly lower than Petitioner’s but it overlaps with Petitioner’s proposed level. Even if we adopted Patent Owner’s proposed level, the outcome would remain the same. C.” slip op. at 9

  • Claim Construction › Threshold & procedure › Whether a term needs construction (O2 Micro)No construction neededNot reached

    “accordance with the ordinary and customary meaning of such claim as understood by one of ordinary skill in the art and the prosecution history pertaining to the patent.” 37 C.F.R. § 42.100(b) (2019). Under the same standard applied by district courts, claim terms acquire their plain and ordinary meaning as would have been understood by a person of ordinary skill in the art at the time of the invention and in the context of the entire patent disclosure. Phillips v. AWH Corp., 415 F.3d 1303, 1313 (Fed. Cir. 2005) (en banc). “There are only two exceptions to this general rule: 1) when a patentee sets out a definition and acts as his own lexicographer, or 2) when the patentee disavows the full scope of a claim term either in the specification or during prosecution.” Thorner v. Sony Comput. Entm’t Am. LLC, 669 F.3d 1362, 1365 (Fed. Cir. 2012). Based on the current record, no terms require explicit construction. See, e.g., Nidec Motor Corp. v. Zhongshan Broad Ocean Motor Co., 868 F.3d 1013, 1017 (Fed. Cir. 2017) (“[W]e need only construe terms ‘that are in controversy, and only to the extent necessary to resolve the controversy’. . . .” (quoting Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999))). D.” slip op. at 9

  • Expert testimonyPetitioner expert creditedPatent owner expert discountedDecided for petitioner

    “does not support Patent Owner’s argument about “undue experimentation” with respect to how to combine the teachings of Koyanagi and Alexander to arrive at the claimed processor module. In the passage containing the quoted testimony that Patent Owner relies upon, Dr. Shanfield testifies as follows: You have obviously got to have a circuit in mind that you're wanting to create a system-level circuit, a module-level circuit; and so you’re going to need to consider which connections you want a TSV connecting to something below. So you don't just slap it together without worrying about what connects to what. On the other hand, the putting together of the -- in Bertin, he describes the putting together of these chips and how that can be done in detail. And that piece of it is -- I guess you could characterize that as something that comes with the process and in itself isn’t something you think specifically about every one of 50,000 connections. They’re all done by the process that he gives an example of. Ex. 2014, 82:4–19.13 Dr. Shanfield’s testimony indicates that artisans of ordinary skill readily would have been able to connect different die circuits together “obviously” with “a circuit in mind . . . to create a system-level circuit, [or] a module-level circuit . . . consider[ing] which [TSV] connections [she] 13 Bertin (Ex. 1009) is employed in the ground discussed below. See infra § II.G. want[s].” See id. As Petitioner similarly argues, “[n]othing in Dr. Shanfield’s testimony, however, suggests that Petitioner ‘slap[ped] together’ Koyanagi and Alexander.” Reply 14; Ex. 1030 ¶ 79 (testifying that Patent Owner quotes his testimony “out of context” and that “at the system or circuit design level, each TSV is an interconnection between specific circuits”).” slip op. at 34

  • Novelty / Anticipation (§102) › Anticipation standard (single reference, every element)UnpatentableUnpatentable

    “Initially, Alexander, a prior art reference, carries a presumption of enablement. Antor Media, 689 F.3d at 1287–1288; Amgen, 314 F.3d at 1355. Patent Owner argues that the presumption does not apply because “for a non-patent publication, such as Alexander, to be presumptively enabling, it must have been “cited by an examiner . . . barring any showing to the contrary by a patent applicant or patentee.” PO Resp. 13 (quoting Antor Media, 689 F.3d at 1288. Patent Owner also argues that “[w]hile it is true that a ‘[e]nablement of an anticipatory reference may be demonstrated by a later reference,’ the Federal Circuit has made clear that the later reference ‘must show that the claimed subject matter was in possession of the public more than one year prior to the applicant’s filing date.’” Id. at 16 (quoting Bristol-Myers Squibb Co. v. Ben Venue Labs., Inc., 246 F.3d 1368, 1379 (Fed. Cir. 2001)).8 Petitioner argues that Patent Owner “mispresents the law.” As Petitioner argues, ‘[a] prior art printed publication does not need to have been ‘cited by an examiner’ to be presumed enabling.” Reply 5. In Corephotonics, 2021 WL 2577597, at *4 (nonprecedential), in the context of AIA trial proceedings, the court held that “regardless of the forum, prior art patents and publications enjoy a presumption of enablement, and the patentee/applicant has the burden to prove nonenablement for such prior art” and that “[i]t was error for the Board to suggest otherwise.” The 1995 publication date of Alexander antedates the’035 patent’s effective filing date of December 5, 2001 by more than six years. See Ex. 1006, 1 (“0-7803-2702-1/95 $ 4.00 © IEEE-1995”); PO Resp. 4 (specifying “December 5, 2001” as “the earliest effective filing date of the ’035 Patent”); Inst Dec. 20–25 (finding the publication date of Alexander is 8 The “more than one year prior to the applicant’s filing date” requirement arises from “anticipation under 35 U.S.C. § 102(b).” See Bristol-Myers Squibb, 246 F.3d at 1379.” slip op. at 14

  Patent outcomesUS RE42,035 unpatentable
  Claim construction§ 102 anticipation§ 103 obviousnesscites Phillips · KSR · Graham
• Samsung Electronics Co., Ltd. / Taiwan Semiconductor Manufacturing Co. Ltd. v. Arbor Global Strategies LLCAll claims unpatentable
  PTAB · Nov 24, 2021 · IPR2020-01020 · APJ Karl D Easthom · IPR · Final written decision

  The Board held claims 1, 5, and 7 anticipated by Alexander, and all challenged claims unpatentable as obvious over the stated combinations.

  RulingsFinal written decision

  • Skill levelSkill level petitioner adoptedDecided for petitioner

    “Patent Owner contends that “a person of ordinary skill in the art . . . would have had a Bachelor’s degree in Electrical Engineering or a related and either (1) two or more years of industry experience; and/or (2) an advanced degree in Electrical Engineering or related field.” PO Resp. 4–5 (citing Ex. 2015 ¶ 33). We adopt Petitioner’s proposed level of ordinary skill in the art as we did in the Institution Decision, which comports with the teachings of the ’035 patent and the asserted prior art. See Inst. Dec. 19. Patent Owner’s proposed level is slightly lower than Petitioner’s but it overlaps with Petitioner’s proposed level. Even if we adopted Patent Owner’s proposed level, the outcome would remain the same. C.” slip op. at 8

  • Claim Construction › Threshold & procedure › Whether a term needs construction (O2 Micro)No construction neededOther

    “accordance with the ordinary and customary meaning of such claim as understood by one of ordinary skill in the art and the prosecution history pertaining to the patent.” 37 C.F.R. § 42.100(b) (2019). Under the same standard applied by district courts, claim terms acquire their plain and ordinary meaning as would have been understood by a person of ordinary skill in the art at the time of the invention and in the context of the entire patent disclosure. Phillips v. AWH Corp., 415 F.3d 1303, 1313 (Fed. Cir. 2005) (en banc). “There are only two exceptions to this general rule: 1) when a patentee sets out a definition and acts as his own lexicographer, or 2) when the patentee disavows the full scope of a claim term either in the specification or during prosecution.” Thorner v. Sony Comput. Entm’t Am. LLC, 669 F.3d 1362, 1365 (Fed. Cir. 2012). Based on the current record, no terms require explicit construction. See, e.g., Nidec Motor Corp. v. Zhongshan Broad Ocean Motor Co., 868 F.3d 1013, 1017 (Fed. Cir. 2017) (“[W]e need only construe terms ‘that are in controversy, and only to the extent necessary to resolve the controversy’. . . .” (quoting Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999))). D.” slip op. at 9

  • Novelty / Anticipation (§102) › Anticipation standard (single reference, every element)UnpatentableUnpatentable

    “In other words, contrary to Patent Owner’s arguments, Alexander need not enable “wafer-thinning technology,” because challenged claims 1, 5, and 7 at issue here do not require that technology. Even so, the ’035 patent admits the “wafer-thinning technology” was known and “developed by Tru-Sci Technologies” prior to the invention. See Ex. 1001, 2:20–30; Prelim. Resp. 18–19 (citing Ex. 1001, 2:20–30; Ex. 2008); Bristol-Myers Squibb Co. v. Ben Venue Labs., Inc., 246 F.3d 1368, 1379 (Fed. Cir. 2001) (“Enablement of an anticipatory reference may be demonstrated by a later reference”). Accordingly, an artisan of ordinary skill reading Alexander 9 Patent Owner does not challenge this preliminary finding in its Response. After a full review of the record, we incorporate and adopt this finding as supported by a preponderance of the evidence. would have considered Alexander enabled for such known technology at the time of the invention.10” slip op. at 16

  • Obviousness (§103) › Motivation to combine / reasonable expectation of successMotivation foundReasonable expectation foundUnpatentable

    “Contrary to these arguments, claim 9 does not recite or require a “stacked die hybrid,” “buffer cells,” any improvements in FPGA reconfiguration times, or a “3D IC.” Claim 9 recites a “reconfigurable computer system” in the preamble, but it does not even recite how the “memory” and “processor” functionally or structurally relate to the “first and second integrated circuit die elements” of the “processor module.” As indicated above, Alexander carries a presumption of enablement as a prior art reference. See Antor Media, 689 F.3d at 1288; Amgen, 314 F.3d at 1355. Alexander employs multi-chip module fabrication techniques “to establish electrical contacts between the interconnect substrate and pads on individual dies.” Ex. 1006, 4. As to obviousness, Petitioner relies on known systems that include a microprocessor, FPGA, and memory. Pet. 22–23 (citing “APA Figure 1”). Petitioner persuasively shows that an artisan of ordinary skill readily could have connected the known FPGA module in a processor and memory system as a substitute for a prior art FPGA, with the system performing as predicted, as evidenced by the block diagram wiring connections in admitted prior art Figure 1 of the ’035 patent, in order to save space and increase processing speed with a reasonable expectation of success. See Pet. 10–11, 21–25 (citing Ex. 1002 ¶¶ 85–93). Patent Owner also alleges thermal issues in Alexander render the claimed combination “inoperable.” PO Resp. 25–28. Again, however, Patent Owner relies on a module or stack of a “3D FPGA with other power hungry components, such as logic dies including microprocessors” to support its arguments. Id. at 27. This argument mischaracterizes the breadth of claims 9, 13, and 15, which do not require a stack that includes a 3D FPGA stack with a microprocessor and memory in that stack, as Petitioner shows and as outlined above. Based on the foregoing discussion, Petitioner shows persuasively that” slip op. at 25

  Patent outcomesUS RE42,035 unpatentable
  Claim construction§ 102 anticipation§ 103 obviousnesscites Phillips · KSR · Graham
• Samsung Electronics Co., Ltd. / Taiwan Semiconductor Manufacturing Co. Ltd. v. Arbor Global Strategies LLCAll claims unpatentable
  PTAB · Nov 24, 2021 · IPR2021-00394 · APJ Karl D Easthom · IPR · Final written decision

  Claims 1, 4, 5, 8, 10, and 13–15 are unpatentable as obvious over Koyanagi and Alexander, and independently over Bertin and Cooke.

  RulingsFinal written decision

  • Skill levelSkill level petitioner adoptedDecided for petitioner

    “Level of Ordinary Skill in the Art Relying on the testimony of Dr. Shanfield, Petitioner contends that [a] person of ordinary skill in the art (“POSITA”) at the time of the alleged invention would have been a person having a Master’s degree in Electrical Engineering, Computer Engineering, or Physics with three to five years of industry experience in integrated circuit design, layout, packaging or fabrication. Ex. 1002 ¶¶ 55–58. A greater level of experience in the relevant field may compensate for less education, and vice versa. Pet. 10.” slip op. at 7

  • Claim Construction › Intrinsic evidence (Phillips canons) › Plain and ordinary meaning to a POSITATerm construed patent owner constructionDecided for patent owner

    “the Board’s preliminary construction only adds ambiguity to the meaning of this term because it requires “a number of vertical contacts that . . . provide contacts on the surface of the memory die,” and further, claim 1 already recites that “‘a second integrated circuit functional element’ has ‘a number of contact points distributed throughout the surfaces of said functional element.’” See id. at 9 (emphasis added). Therefore, Patent Owner offers the following “suggest[ion]”: “To the extent that the Board finds it necessary to mention contacts in the context of the claimed ‘memory array,’ Patent Owner suggests that the Board use the term ‘a number of vertical contacts distributed throughout the surface of and traversing the memory die.’” PO Resp. 8 (emphasis added). For reasons discussed further below and in the Institution Decision, the record, including the specification, supports Patent Owner’s suggestion, and we determine that Patent Owner’s claim construction suggestion is materially the same as the preliminary claim construction set forth in the Institution Decision. See, e.g., Ex. 1001, 2:41–44 (“[S]ince these differing die do not require wire bonding to interconnect, it is now also possible to place interconnect pads throughout the total area of the various die rather than just around their periphery.”) (emphasis added); Inst. Dec. 24–25. In addition to Patent Owner’s suggestion above, Patent Owner also argues that “the term ‘a memory array functional to accelerate external memory references to the processing element’ means ‘a memory array that allows the parallel loading of data through buffer cells.’” PO Resp. 6 (emphasis added). Patent Owner asserts that “[i]n its preliminary response, Patent Owner advocated that this term should be accorded its plain and ordinary meaning.” PO Resp. 5. It is not clear if Patent Owner maintains (i.e., in its Response) that the phrase carries its plain and ordinary meaning.9 In any event, the record does not support Patent Owner’s proposed requirement for “buffer cells” under the plain and ordinary meaning of the “functional to accelerate” clause or under lexicography principles, prosecution history or otherwise, for the reasons advanced by Petitioner and as addressed below. In line with Patent Owner’s suggestion and as we similarly determined in the Institution Decision, the “functional to accelerate” limitations require “a number of vertical contacts distributed throughout the surface of and traversing the memory die in a vertical direction (vias) to allow multiple short paths for data transfer between the memory and processor.” See Ex. 1001, Fig. 4 (showing numerous contact points); Inst. Dec. 25 (materially similar construction); PO Resp. 8 (Patent Owner’s suggestion). We adopt and incorporate the claim construction findings in the Institution Decision, much of which we repeat here for completeness. See Inst. Dec. 19–25. slip op. at 10

  • Obviousness (§103) › Graham factors (scope of art, differences, level of skill)UnpatentableUnpatentable

    “As Petitioner argues, the combined Koyanagi and Alexander system mimics the ’951 patent’s disclosure by employing stacked dies with a “large number of contact points distributed throughout the surfaces of the dies.” Pet. 29; see also supra notes 14, 16. Petitioner also provides evidence that an artisan of ordinary skill would have known of several advantages in stacking 3D chips with multiple vias including “high packing density,” “high speed,” “parallel signal processing,” and “integration of many functions on a single chip.” Id. at 4 (citing Ex. 1010, 1704; Ex. 1002 ¶ 39). Petitioner points to Koyanagi’s “key benefit” as “enab[ling]large data bandwidth in vertical data transfers” (Ex. 1007, 17) to mitigate bus bottlenecks, further showing that multiple vias provide for parallel signal processing and increased processing speed in stacked dies as found above. See Pet. 30 (citing Ex. 1007, 17, 19); supra § II.C (Claim Construction); supra notes 14, 16. In other words, Petitioner shows how the combined teachings of Koyanagi and Alexander teach or suggest to an artisan of ordinary skill the accelerate clause in the challenged claims by providing a large number of short parallel via connections, thereby functionally enabling large data bandwidths and parallel processing, as was well-known at the time of the invention. See Pet. 4, 17–23, 28–29; Ex. 1007, 17–18; supra notes 14, 16; Reply 15–17; In re Graves, 69, F.3d 1147, 1152 (Fed. Cir. 1995)(holding that “Rockwell . . . anticipates claim 4, even if it does not specifically disclose simultaneous monitoring of the output points, if simultaneous or parallel monitoring is within the knowledge of a skilled artisan”).” slip op. at 35

  • Obviousness (§103) › Motivation to combine / reasonable expectation of successMotivation foundReasonable expectation foundDecided for petitioner

    “As Petitioner also argues and as summarized above, the Petition “provide[s] a detailed explanation of how Koyanagi and Alexander would have been combined to disclose each limitation of the Challenged Claims and why a POSITA would have been motivated to combine them––‘to create a 3D reconfigurable processor module with improved performance and areaefficiency.’” Reply 16 (quoting Pet. 17). By way of example, Petitioner’s annotated Figure 1M, which represents combined teachings of Koyanagi and Alexander, shows how to connect the dies together using conductive vias as challenged claim 1 requires. Petitioner also provides persuasive detail with respect to the remaining challenged claims at issue in this section (i.e., claims 4, 5, 8, 10, 13–15). See Pet. 31–46. By teaching similar stacking techniques for similar circuits including the use of conductive vias with logic dies including FPGAs, memory, and microprocessors, Koyanagi and Alexander collectively evidence a reasonable expectation of success without undue experimentation in arriving at the claimed invention. See Otsuka Pharm. Co., v. Sandoz, Inc., 678 F.3d 1280, 1296 (Fed. Cir. 2012) (“The inventor's own path itself never leads to a conclusion of obviousness; that is hindsight. What matters is the path that the person of ordinary skill in the art would have followed, as evidenced by the pertinent prior art.”). In other words, Petitioner shows that the claimed invention involves a routine combination of familiar elements to yield predictable results, namely combining Alexander’s known 2D-FPGA die with Koyanagi’s similar die stack, or simply substituting Alexander’s known 2D-FPGA die in place of a similar DRAM memory die in the die stack of Koyanagi, with the coupled circuits functioning with processing speed gains and other benefits as expected. See Pet. 27–29; Reply 14 (citing KSR, 550 U.S. at 416 (“The combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results.”)).” slip op. at 42

  Patent outcomesUS 7,282,951 unpatentable
  Claim construction§ 103 obviousnesscites Phillips · KSR · Graham
  Patents in suitUS 7,282,951
• Samsung Electronics Co., Ltd. / Taiwan Semiconductor Manufacturing Co. Ltd. v. Arbor Global Strategies LLCAll claims unpatentable
  PTAB · Nov 24, 2021 · IPR2020-01021 · APJ Karl D Easthom · IPR · Final written decision

  Claims 1, 4, 5, 8, 10, and 13–15 are unpatentable as obvious over Koyanagi and Alexander, and independently over Bertin and Cooke.

  RulingsFinal written decision

  • Skill levelSkill level petitioner adoptedDecided for petitioner

    “Level of Ordinary Skill in the Art Relying on the testimony of Dr. Shanfield, Petitioner contends that [a] person of ordinary skill in the art (“POSITA”) at the time of the alleged invention would have been a person having a Master’s degree in Electrical Engineering, Computer Engineering, or Physics with three to five years of industry experience in integrated circuit design, layout, packaging or fabrication. Ex. 1002 ¶¶ 55–58. A greater level of experience in the relevant field may compensate for less education, and vice versa.” slip op. at 7

  • Claim Construction › Intrinsic evidence (Phillips canons) › Plain and ordinary meaning to a POSITATerm construed patent owner constructionDecided for patent owner

    “the Board’s preliminary construction only adds ambiguity to the meaning of this term because it requires “a number of vertical contacts that . . . provide contacts on the surface of the memory die,” and further, claim 1 already recites that “‘a second integrated circuit functional element’ has ‘a number of contact points distributed throughout the surfaces of said functional element.’” See id. at 9 (emphasis added). Therefore, Patent Owner offers the following “suggest[ion]”: “To the extent that the Board finds it necessary to mention contacts in the context of the claimed ‘memory array,’ Patent Owner suggests that the Board use the term ‘a number of vertical contacts distributed throughout the surface of and traversing the memory die.’” PO Resp. 8 (emphasis added). For reasons discussed further below and in the Institution Decision, the record, including the specification, supports Patent Owner’s suggestion, and we determine that Patent Owner’s claim construction suggestion is materially the same as the preliminary claim construction set forth in the Institution Decision. See, e.g., Ex. 1001, 2:41–44 (“[S]ince these differing die do not require wire bonding to interconnect, it is now also possible to place interconnect pads throughout the total area of the various die rather than just around their periphery.”) (emphasis added); Inst. Dec. 24–25. slip op. at 10

  • Obviousness (§103) › Motivation to combine / reasonable expectation of successMotivation foundReasonable expectation foundUnpatentable

    “These claim construction arguments that rely on “buffer cells” fail for the reasons noted above, the challenged claims do not require buffer cells. See supra § II.C (Claim Construction). As summarized above, the ’951 patent describes in its abstract and other places, including in reference to Figure 4, providing accelerated data transfers and reconfiguration without buffer cells by using numerous short vias to connect circuits in the stacked dies. See id. As outlined above, Petitioner provides ample motivation supported by the record as to “how and why” an artisan of ordinary skill would have combined the stacked die features of Koyanagi with the similar features of Alexander, to include the well-known FGPA, and it shows how the vertical interconnections employed in both references track the disclosed invention to obtain the claimed acceleration. See, e.g., Pet. 29 (annotating Koyanagi’s Figure 1). Wiring similar well-known circuits with short conductive vias instead of long conventional conductors would have been obvious and well-within the ordinary skill of an artisan, motivated by many reasons (for example, speed/bandwidth gains, compactness, power consumption, FPGA design flexibility) as the Petition shows and as Koyanagi and Alexander suggest as discussed above. See, e.g., Ex. 1006, Abstract (describing a “fabrication technology” and “expected manufacturing yield”), 1 (describing “10,000 solder bumps” “to establish the vertical interconnections” and “enabling electrical interconnections between the two sides of the die,” by “adapting multi-chip module (MCM) fabrication technology”); Ex. 1007, 17 (similarly describing MCM technology and using 10,000 (105) “interconnections per chip” to make 3D MCMs “fabricated using our new integration technology”), Fig. 6 (showing “Fabrication sequence of 3D LSI”).” slip op. at 37

  • Obviousness (§103) › Motivation to combine / reasonable expectation of success › Teaching awayTeaching away not foundDecided for petitioner

    “However, as Petitioner argues and as Dr. Chakrabarty confirms, using many short vertical conductive vias (e.g., TSVs) versus long conductive runs “reduces power consumption and improves heat removal (because TSVs also serve as heat pipes).” Reply 17 (citing Ex. 1007, 17). In other words, Dr. Chakrabarty acknowledges that [w]hat Koyanagi says is actually obvious to anybody who is skilled in the art. Anybody who is skilled in the art would know that via is conductive. It is a conductor for both electricity and for heat. And therefore, if you have lots of vias, you’re going to take out the heat. Ex. 1035, 256:9–15 (emphasis added); see Reply 17 (partially quoting Ex. 1035, 256:9–15). Therefore, as Petitioner persuasively argues, rather than ignoring thermal issues or deterring a person of skill in the art from combining Koyanagi and Alexander, “a POSITA would have been motivated to find a solution to the alleged thermal issues, and would have recognized that a large number of 3D interconnections between dies contribute to such a solution.” See Reply 21 (citing Ex. 1030 ¶ 53).” slip op. at 50

  Patent outcomesUS 7,282,951 unpatentable
  Claim construction§ 103 obviousnesscites Phillips · KSR · Graham
  Patents in suitUS 7,282,951
• Samsung Electronics Co., Ltd. / Taiwan Semiconductor Manufacturing Co. Ltd. v. Arbor Global Strategies LLCAll claims unpatentable
  PTAB · Nov 24, 2021 · IPR2021-00393 · APJ Sharon Fenick · IPR · Final written decision

  Claims 13, 14, 16–23, and 25–30 are unpatentable as obvious over Koyanagi and Cooke and over Bertin and Cooke.

  RulingsFinal written decision

  • Skill levelSkill level petitioner adoptedDecided for petitioner

    “Level of Ordinary Skill in the Art Relying on the testimony of Dr. Shanfield, Petitioner contends that [a] person of ordinary skill in the art (“POSITA”) at the time of the ’226 Patent would have been a person having a Master’s degree in Electrical Engineering, Computer Engineering, or Physics with three to five years of industry experience in integrated circuit design, layout, packaging or fabrication. Ex. 1002 ¶¶ 45–48. A greater level of experience in the relevant field may compensate for less education, and vice versa.” slip op. at 7

  • Claim Construction › Functional claiming / §112(f) means-plus-function › Whether §112(f) applies (Williamson, nonce words)§112(f) appliesDecided for petitioner

    “13.4 in claim 13) and “means for updating the plurality of configuration logic cells within one clock cycle” (limitation 22.4 in claim 22) are means-plus-function limitations and should be construed as per 35 U.S.C. § 112, ¶ 6. Pet. 9; PO Resp. 6–7. Both of these limitations listed above recite “means” and further recite a function, thus creating a presumption that 35 U.S.C. § 112, ¶ 6 applies. See 35 U.S.C. § 112, ¶ 6 (“An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.”); see also Williamson v. Citrix Online, LLC, 792 F.3d 1339, 1349 (Fed. Cir. 2015) (en banc in relevant part) (quoting Personalized Media Commc’ns, LLC v. Int’l Trade Comm’n, 161 F.3d 696, 703 (Fed. Cir. 1998)) (holding that “use of the word ‘means’ creates a presumption that § 112, ¶ 6 applies”). We agree with the parties that these limitations are means-plus-function limitations subject to 35 U.S.C. § 112, ¶ 6.” slip op. at 9

  • Claim Construction › Intrinsic evidence (Phillips canons) › Plain and ordinary meaning to a POSITATerm construed board ownDecided for petitioner

    “Patent Owner, in focusing on this portion of the ’226 patent disclosure, does not adequately explain why buffer cells and configuration memory cells must be included in the proper construction of “wide configuration data port,” and seeks to import a functional description of the use of a wide configuration data port (“that allows parallel updating of logic cells in a programmable array through use of buffer cells”) into the claim construction. PO Resp. 11–14; PO Sur-reply 2–4. While the discussion in the ’226 patent describes an example of a wide configuration data port used in a specific way that aligns with Patent Owner’s proposal (Ex. 1001, 4:45– 59), other examples of the use of a wide configuration data port are included (id. at 4:59–65), and therefore we do not agree that one of ordinary skill would understand this use to be part of the construction of the term. We agree with Petitioner that the proper construction of the term does not require buffer cells to be specifically described. See Pet. Reply 6–9. Rather, we note that the specification of the ’226 patent contrasts loading of data to an FPGA in a byte serial fashion through a narrow port, which “results in [] long reconfiguration times,” with the use of a wide configuration data port, and therefore we determine that one of ordinary skill would understand the wide configuration data port, in contrast to the byte serial “relatively narrow” port, to include parallel connections between cells in the dies. See Ex. 1001, 4:3–9. This additionally is consistent with certain arguments by Patent Owner, for example in the Patent Owner’s Response, which opens with a discussion of the “inventive” processor’s arrangement of die-area contacts, such as through-silicon vias, “into a wide configuration data port” and we find that description more consistent with the proper construction of this term. PO Resp. 1–2; see also id. at 8 (“[T]he ’226 Patent specifically identifies that the wide configuration data port reconfigures both a programmable array and/or logic cells in one clock cycle because it can communicate with many cells (which form an ‘array’) in parallel, and is therefore considered ‘wide.’”)” slip op. at 14

  • Claim Construction › Functional claiming / §112(f) means-plus-function › Corresponding structure / algorithm (indefinite if none)Term construed board ownDecided for petitioner

    “While corresponding structure need not include all things necessary to enable the claimed invention to work, it must include all structure that actually performs the recited function.” Default Proof Credit Card Sys. Inc. v. Home Depot U.S.A., Inc., 412 F.3d 1291, 1298 (Fed. Cir. 2005). Conversely, structural features that do not actually perform the recited function do not constitute corresponding structure and thus do not serve as claim limitations. Chiuminatta Concrete Concepts, Inc. v. Cardinal Indus., Inc., 145 F.3d 1303, 1308–09, (Fed. Cir. 1998); see B. Braun Med., Inc. v. Abbott Labs., 124 F.3d 1419, 1424 (Fed. Cir. 1997) (“[S]tructure disclosed in the specification is ‘corresponding’ structure only if the specification or prosecution history clearly links or associates that structure to the function recited in the claim.”). Given our construction of wide configuration data port, Patent Owner’s argument that the corresponding structure for this limitation must require that buffer cells on one die element are connected in parallel to cells on another die element is based on the description of the use of buffer cells as used in the updating of the FPGA while it is in operation. PO Supp. Br. 3 (citing Ex. 1001, 4:50–54, Fig. 5). However, we note that this description is followed by the disclosure that “[t]he buffer cells 88 are preferably a portion of the memory die 66.” Ex. 1001, 4:50–54. It does not appear, therefore, that buffer cells are always a portion of the memory die, or are required when the FPGA is not in operation, and thus we decline to require in the corresponding structure that they be specified to be on a specific separate die element. Rather, we find that what is disclosed as actually performing the recited function of “reconfiguring the programmable array within one clock cycle” is “a wide configuration data port and contact points formed throughout the area of the first integrated circuit die element and another integrated circuit die element.” The support for this is found in the ’266 patent’s comparison of the long reconfiguration times through a narrow port (Ex. 1001, 4:3–9) with the time to reconfigure through a wide configuration data port with a significantly increased number of connections (id. at 4:45– 65), and the implementation of this in a module that has multiple dies “which have a number of corresponding contact points, or holes, 70 formed throughout the area of the [die] package” (id. at 4:9–20). The use of a wide configuration data port, as per our construction, implicates two die elements. This was reflected in our preliminary claim construction, for which the corresponding structure described “contact points distributed through the slip op. at 18

  Patent outcomesUS 6,781,226 unpatentable
  Claim construction§ 103 obviousnesscites Phillips · KSR · Graham
  Patents in suitUS 6,781,226
• Samsung Electronics Co., Ltd. / Taiwan Semiconductor Manufacturing Co. Ltd. v. Arbor Global Strategies LLCAll claims unpatentable
  PTAB · Nov 24, 2021 · IPR2020-01022 · APJ Sharon Fenick · IPR · Final written decision

  Claims 13, 14, 16–23, and 25–30 are unpatentable as obvious over Koyanagi and Cooke, and over Bertin and Cooke.

  RulingsFinal written decision

  • Skill levelSkill level petitioner adoptedDecided for petitioner

    “Level of Ordinary Skill in the Art Relying on the testimony of Dr. Shanfield, Petitioner contends that [a] person of ordinary skill in the art (“POSITA”) at the time of the ’226 Patent would have been a person having a Master’s degree in Electrical Engineering, Computer Engineering, or Physics with three to five years of industry experience in integrated circuit design, layout, packaging or fabrication. Ex. 1002 ¶¶ 45–48. A greater level of experience in the relevant field may compensate for less education, and vice versa. Pet. 7–8. Patent Owner asserts that [a] person of ordinary skill in the art (“POSITA”) around December 5, 2001 (the earliest effective filing date of the ’226 6 No argument or evidence regarding secondary considerations has been presented in this proceeding. Patent) would have had a Bachelor’s degree in Electrical Engineering or a related field, and either (1) two or more years of industry experience; and/or (2) an advanced degree in Electrical Engineering or related field. PO Resp. 5–6 (citing Ex. 2009 ¶¶ 31–34). As we did in the Decision on Institution, we adopt Petitioner’s proposed level of ordinary skill in the art, which comports with the teachings of the ’226 patent and the asserted prior art. See Dec. on Inst. 18–19. Patent Owner’s proposed level is lower but it overlaps with Petitioner’s proposed level. Even if we adopted Patent Owner’s proposed level, the outcome would remain the same. C.” slip op. at 7

  • Claim Construction › Functional claiming / §112(f) means-plus-function › Whether §112(f) applies (Williamson, nonce words)§112(f) appliesDecided for petitioner

    “Both of these limitations listed above recite “means” and further recite a function, thus creating a presumption that 35 U.S.C. § 112, ¶ 6 applies. See 35 U.S.C. § 112, ¶ 6 (“An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.”); see also Williamson v. Citrix Online, LLC, 792 F.3d 1339, 1349 (Fed. Cir. 2015) (en banc in relevant part) (quoting Personalized Media Commc’ns, LLC v. Int’l Trade Comm’n, 161 F.3d 696, 703 (Fed. Cir. 1998)) (holding that “use of the word ‘means’ creates a presumption that § 112, ¶ 6 applies”). We agree with the parties that these limitations are means-plus-function limitations subject to 35 U.S.C. § 112, ¶ 6.” slip op. at 9

  • Claim Construction › Intrinsic evidence (Phillips canons) › Plain and ordinary meaning to a POSITATerm construed board ownDecided for petitioner

    “Patent Owner, in focusing on this portion of the ’226 patent disclosure, does not adequately explain why buffer cells and configuration memory cells must be included in the proper construction of “wide configuration data port,” and seeks to import a functional description of the use of a wide configuration data port (“that allows parallel updating of logic cells in a programmable array through use of buffer cells”) into the claim construction. PO Resp. 11–14; PO Sur-reply 2–4. While the discussion in the ’226 patent describes an example of a wide configuration data port used in a specific way that aligns with Patent Owner’s proposal (Ex. 1001, 4:45– 59), other examples of the use of a wide configuration data port are included (id. at 4:59–65), and therefore we do not agree that one of ordinary skill would understand this use to be part of the construction of the term. We agree with Petitioner that the proper construction of the term does not require buffer cells to be specifically described. See Pet. Reply 6–9. Rather, we note that the specification of the ’226 patent contrasts loading of data to an FPGA in a byte serial fashion through a narrow port, which “results in [] long reconfiguration times,” with the use of a wide configuration data port, and therefore we determine that one of ordinary skill would understand the wide configuration data port, in contrast to the byte serial “relatively narrow” port, to include parallel connections between cells in the dies. See Ex. 1001, 4:3–9. This additionally is consistent with certain arguments by Patent Owner, for example in the Patent Owner’s Response, which opens with a discussion of the “inventive” processor’s arrangement of die-area contacts, such as through-silicon vias, “into a wide configuration data port” and we find that description more consistent with the proper construction of this term. PO Resp. 1–2; see also id. at 8 (“[T]he ’226 Patent specifically identifies that the wide configuration data port reconfigures both a programmable array and/or logic cells in one clock cycle because it can communicate with many cells (which form an ‘array’) in parallel, and is therefore considered ‘wide.’”)” slip op. at 14

  • Claim Construction › Functional claiming / §112(f) means-plus-function › Corresponding structure / algorithm (indefinite if none)Term construed board ownDecided for petitioner

    “While corresponding structure need not include all things necessary to enable the claimed invention to work, it must include all structure that actually performs the recited function.” Default Proof Credit Card Sys. Inc. v. Home Depot U.S.A., Inc., 412 F.3d 1291, 1298 (Fed. Cir. 2005). Conversely, structural features that do not actually perform the recited function do not constitute corresponding structure and thus do not serve as claim limitations. Chiuminatta Concrete Concepts, Inc. v. Cardinal Indus., Inc., 145 F.3d 1303, 1308–09, (Fed. Cir. 1998); see B. Braun Med., Inc. v. Abbott Labs., 124 F.3d 1419, 1424 (Fed. Cir. 1997) (“[S]tructure disclosed in the specification is ‘corresponding’ structure only if the specification or prosecution history clearly links or associates that structure to the function recited in the claim.”). Given our construction of wide configuration data port, Patent Owner’s argument that the corresponding structure for this limitation must require that buffer cells on one die element are connected in parallel to cells on another die element is based on the description of the use of buffer cells as used in the updating of the FPGA while it is in operation. PO Supp. Br. 3 (citing Ex. 1001, 4:50–54, Fig. 5). However, we note that this description is followed by the disclosure that “[t]he buffer cells 88 are preferably a portion of the memory die 66.” Ex. 1001, 4:50–54. It does not appear, therefore, that buffer cells are always a portion of the memory die, or are required when the FPGA is not in operation, and thus we decline to require in the corresponding structure that they be specified to be on a specific separate die element. Rather, we find that what is disclosed as actually performing the recited function of “reconfiguring the programmable array within one clock cycle” is “a wide configuration data port and contact points formed throughout the area of the first integrated circuit die element and another integrated circuit die element.” The support for this is found in the ’266 patent’s comparison of the long reconfiguration times through a narrow port (Ex. 1001, 4:3–9) with the time to reconfigure through a wide configuration data port with a significantly increased number of connections (id. at 4:45– 65), and the implementation of this in a module that has multiple dies “which have a number of corresponding contact points, or holes, 70 formed throughout the area of the [die] package” (id. at 4:9–20). The use of a wide configuration data port, as per our construction, implicates two die elements. This was reflected in our preliminary claim construction, for which the corresponding structure described “contact points distributed through the slip op. at 18

  Patent outcomesUS 6,781,226 unpatentable
  Claim construction§ 103 obviousnesscites Phillips · KSR · Graham
  Patents in suitUS 6,781,226
• Juniper Networks, Inc. v. Correct Transmission, LLCInstitution denied
  PTAB · Nov 19, 2021 · IPR2021-00984 · APJ Bryan F Moore · IPR · Institution

  The Board denied institution on all challenged claims because the petition did not show a reasonable likelihood that the asserted obviousness grounds taught or suggested the claimed responsive fragmentation.

  RulingsInstitution decision

  • PTAB / AIA Trials › Institution threshold (reasonable likelihood / more likely than not)Institution denied meritsInstitution denied

    “Applying those standards, and upon consideration of the information presented in the Petition, Preliminary Response, and Reply, we determine that Petitioner has not demonstrated a reasonable likelihood of prevailing with respect to at least one Challenged Claim of the ’669 patent. See 35 U.S.C. § 314; 37 C.F.R. § 42.4(a). Accordingly, we do not institute an inter partes review of the ’669 patent.” slip op. at 2

  • Skill levelSkill level petitioner adoptedOther

    “would have had a bachelor’s degree in electrical engineering, computer engineering, computer science, or a closely related field, and one to two years of experience in the design and development of network communication systems. Alternatively, a POSITA would have a master’s degree or similar post-graduate work in electrical engineering, computer engineering, computer science, or a closely related field, and fewer years of design and development experience. Pet. 5–6 (citing Ex. 1003 ¶¶ 59–63). “Patent Owner takes no position with respect to Petitioner’s proposed level of skill.” Prelim. Resp. 37. We regard Petitioner’s proposed definition as reasonable, and consistent with the prior art before us. See In re GPAC Inc., 57 F.3d 1573, 3 At this stage of the proceeding, Patent Owner has not presented objective evidence of non-obviousness. 1579 (Fed. Cir. 1995) (determining that the Board of Patent Appeals and Interferences did not err in concluding that the level of ordinary skill in the art was best determined by the references of record). Accordingly, we apply the level of skill set forth above, which also is consistent with the testimony of Dr. Yang. Ex. 1003 ¶¶ 59–63.” slip op. at 7

  • Claim Construction › Threshold & procedure › Whether a term needs construction (O2 Micro)No construction neededOther

    “C. Claim Construction Neither Petitioner nor Patent Owner proposes any claim terms for construction. Pet. 6 (“Petitioner construes each term as having its ordinary and customary meaning.”); Prelim. Resp. 11 (“Patent Owner does not propose any claim term departs from its ordinary and customary meaning.”). We do not find that the express construction of any term is necessary for this decision. See Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999) (“[O]nly those terms need be construed that are in controversy, and only to the extent necessary to resolve the controversy.”); Nidec Motor Corp. v. Zhongshan Broad Ocean Motor Co., 868 F.3d 1013, 1017 (Fed. Cir. 2017) (applying Vivid Techs. in the context of an inter partes review).” slip op. at 8

  • Obviousness (§103) › Motivation to combine / reasonable expectation of success › HindsightNot shown unpatentableMotivation not foundNot shown unpatentable

    “While not showing a teaching away, the above statement in Sourani contrasting stop points and fragmentation does show that one of ordinary skill in the art reading Sourani would know that the stop points in Sourani are not intended to be fragments. Petitioner has not explained sufficiently why, despite this contrast, one of ordinary skill would use fragmentation with the system of Sourani.” slip op. at 14

  Claim construction§ 102 anticipation§ 103 obviousnessDiscretionary denialcites KSR · Graham
  Patents in suitUS 6,876,669
• Apple, Inc. v. Corephotonics Ltd.No claims unpatentable
  PTAB · Nov 8, 2021 · IPR2020-00906 · APJ John F Horvath · IPR · Final written decision

  Claims 19–22 were not shown unpatentable because Petitioner did not establish that Ogata’s lens could be scaled for Parulski’s camera with a reasonable expectation of success.

  RulingsFinal written decision

  • Expert testimonyDecided for patent owner

    “first embodiment lens and the data entered into the “Lens Editor Data” spreadsheet are noticeable. First, the Abbe number for the third lens element is 42.72 in Ogata’s first embodiment lens and 26.5 (i.e., 38% smaller) in the “Lens Data Editor” spreadsheet. Compare Ex. 1026, 7:46, with Ex. 1021, 36. Second, the data for the fourth and tenth aspherical surfaces are noticeably different. For example, the fourth order term (A4) for the fourth aspherical surface is 0.66 x 10-4 in Ogata’s first embodiment lens and 151.69 x 10-4 (i.e., 0.015) in the “Lens Data Editor” spreadsheet. Compare Ex. 1026, 7:55, with Ex. 1021, 36. Neither Petitioner nor Dr. Sasián explain these discrepancies.” slip op. at 15

  • Strike new argumentNew argument disregardedDecided for patent owner

    “We agree with Patent Owner. The Petition contends that a person of ordinary skill in the art would have known that Ogata’s lens (using glass lens elements) could have been scaled to focus an image onto a 1/2.5” image sensor for use in Parulski’s camera. See Pet. 24–30; Ex. 1021, 36. Petitioner’s reply evidence and argument is not introduced to support that contention but a different contention—that a person of ordinary skill in the art would have known that Ogata’s lens could have been redesigned using aspheric plastic lens elements to focus an image onto a 1/3” image sensor. See n.11, supra. This is a new contention that does not support Petitioner’s 11 We note that Dr. Sasián’s analysis discloses how Kawamura’s lens can be modified by replacing the spherical glass lens elements with aspherical plastic lens elements, moving the aperture stop to the first lens element, changing the F number to 2.8, and reducing the effective focal length to focus an image onto a 1/3” image sensor rather than a 1/2.5” image sensor. See Ex. 1039 ¶¶ 25–30; App’x, 17–18. Dr. Sasián also opines that although this analysis illustrates how Kawamura’s lens could have been modified, a person skilled in the art “would have recognized that Ogata could have been similarly adjusted to yield a miniaturized form-factor.” Id. ¶ 25. because it is a new and untimely contention, we do not consider it further. See Consolidated Trial Practice Guide (Nov. 2019)12 (“Petitioner may not submit new evidence or argument in reply that it could have presented earlier, e.g., to make out a prima facie case of unpatentability.”); see also Ariosa Diagnostics v. Verinata Heath, Inc., 805 F.3d 1359, 1368 (Fed. Cir. 2015) (“The Board must make judgments about . . . when a Reply contention crosses the line from the responsive to the new.”); Intelligent Bio-Sys., Inc. v. Illumina Cambridge Ltd., 821 F.3d at 1359, 1369–70 (Fed. Cir. 2016) (affirming the Board’s rejection of a reply argument presenting an “entirely new rationale to explain why one of skill in the art would have been motivated to combine” prior art references); Henny Penny Corp. v. Frymaster LLC, 938 F.3d 1324, 1330–31 (Fed. Cir. 2019) (affirming the Board’s rejection of a reply argument presenting an “entirely new rationale” for why a claim would have been obvious).” slip op. at 18

  • Obviousness (§103) › Motivation to combine / reasonable expectation of successNot shown unpatentableReasonable expectation not foundNot shown unpatentable

    “first embodiment lens and the data entered into the “Lens Editor Data” spreadsheet are noticeable. First, the Abbe number for the third lens element is 42.72 in Ogata’s first embodiment lens and 26.5 (i.e., 38% smaller) in the “Lens Data Editor” spreadsheet. Compare Ex. 1026, 7:46, with Ex. 1021, 36. Second, the data for the fourth and tenth aspherical surfaces are noticeably different. For example, the fourth order term (A4) for the fourth aspherical surface is 0.66 x 10-4 in Ogata’s first embodiment lens and 151.69 x 10-4 (i.e., 0.015) in the “Lens Data Editor” spreadsheet. Compare Ex. 1026, 7:55, with Ex. 1021, 36. Neither Petitioner nor Dr. Sasián explain these discrepancies.” slip op. at 15

  Patent outcomesUS 10,225,479 not shown unpatentable
  § 103 obviousness
  Patents in suitUS 10,225,479

Holdings, summaries, rulings, issues, outcomes, winners and claim constructions shown for a decision were generated by a large language model reading the opinion. They are a guide to the decision, not the decision. Confirm every one against the court's own text before relying on it. Outcomes read from the patent owner’s side. Party names are extracted from the decision and are missing on about 900 short Director denials and scans, which carry the trial number instead.