- Xilinx, Inc. v. Arbor Global Strategies, LLCAll claims unpatentablePTAB · Mar 2, 2022 · IPR2021-00736 · APJ Karl D Easthom · IPR · Final written decision
Claims 1, 2, 4–6, and 8–29 are unpatentable as obvious under §103 based on the listed combinations of prior art.
RulingsFinal written decision- Obviousness (§103) › Motivation to combine / reasonable expectation of successUnpatentableMotivation foundUnpatentable
“Accordingly, as we noted in the Institution Decision, in light of Lin’s teachings and absent explicit explanation during prosecution by the Examiner, the rejection and reasons for allowance provide further support the understanding that the “functional to accelerate” limitations require a number of contacts extending throughout the thickness of the wafers in a vertical direction (vias) within the periphery of the die to allow multiple short paths for data transfer between the memory and process[ing element].” slip op. at 19
- Expert testimonyPetitioner expert creditedDecided for petitioner
“Souri’s support for TSV issues is a citation to “Ex. 2014 at 85, 97, 90.” Ex. 2011 ¶ 82. Patent Owner provides the same citation without any explanation of the citation. PO Resp. 41. This amounts to the same type of incorporation-by-reference of pages of evidence that Patent Owner attributes to Petitioner. Also, the cited three pages of Exhibit 2014 are in the middle of an industry article, and the pages are densely packed two-column pages that facially appear to have at least the same number of words in some of the complained-about citations to multiple paragraphs that Petitioner provides to Dr. Souri’s Reply Declaration. Here, Patent Owner leaves it to the Board to dig into the cited pages of Exhibit 2014 to find the alleged TSV interconnection issues and place it in context to the background information in the whole article. In reaching our decision, we exercised judgment as to all the evidence cited by the parties for its relevance, context, and substance, and weighed it accordingly.” slip op. at 110
Patent outcomesUS 7,282,951 unpatentable§ 103 obviousnesscites KSR · GrahamPatents in suitUS 7,282,951 - Xilinx, Inc. v. Arbor Global Strategies, LLCAll claims unpatentablePTAB · Mar 2, 2022 · IPR2020-01568 · APJ Karl D Easthom · IPR · Final written decision
Claims 1, 2, 4–6, and 8–29 are unpatentable as obvious under § 103 based on the listed combinations of prior art.
RulingsFinal written decision- Obviousness (§103) › Graham factors (scope of art, differences, level of skill)UnpatentableUnpatentable
“Accordingly, as we noted in the Institution Decision, in light of Lin’s teachings and absent explicit explanation during prosecution by the Examiner, the rejection and reasons for allowance provide further support the understanding that the “functional to accelerate” limitations require a number of contacts extending throughout the thickness of the wafers in a vertical direction (vias) within the periphery of the die to allow multiple short paths for data transfer between the memory and process[ing element].” slip op. at 19
Patent outcomesUS 7,282,951 unpatentable§ 103 obviousnesscites KSR · GrahamPatents in suitUS 7,282,951 - Xilinx, Inc. v. Arbor Global Strategies, LLCAll claims unpatentablePTAB · Mar 2, 2022 · IPR2021-00735 · APJ Barbara A Benoit · IPR · Final written decision
Claims 1–6 and 26–31 are unpatentable as obvious over the stated combinations of Zavracky, Chiricescu, and Akasaka, with Satoh or Alexander added for dependent claims.
RulingsFinal written decision- Skill levelSkill level petitioner adoptedDecided for petitioner
“B. Level of Ordinary Skill in the Art The parties dispute the level of ordinary skill in the art. The level of” slip op. at 9
- Claim Construction › Threshold & procedure › Whether a term needs construction (O2 Micro)No construction neededOther
“C. Claim Construction In an inter partes review, the Board construes each claim “in” slip op. at 10
- Obviousness (§103) › Motivation to combine / reasonable expectation of successMotivation foundReasonable expectation foundUnpatentable
“articulated reasoning to support a conclusion of obviousness. PO Resp. 2–3, 23–39; PO Sur-reply 10–14. (i) Alleged Misrepresentation of Chiricescu First, Patent Owner contends that “Petitioner misrepresents Chiricescu to allege motivation to combine Zavracky and Chiricescu.” PO Resp. 24–25 (Section VI.A.3(a)). Patent Owner specifically asserts that Chiricescu does not employ Zavracky’s principles, does not utilize Zavracky’s principles to improve reconfiguration time, and “does not employ Zavracky’s die-area vertical interconnections to connect a memory die to an FPGA, and no die-area vertical is involved whatsoever in reconfiguring Chiricescu’s FPGA.” PO Resp. 24 (citing Pet. 18–19, Ex. 1004, 232 (Exhibit page 1), 234 (Exhibit page 3); Ex. 2011 ¶ 6117). The record does not support this line of argument. Chiricescu’s Abstract indicates the paper describes “[t]he architecture of a 3-dimensional FPGA for reconfigurable computing machines” and “is based on a novel 3-D circuit technology developed at Northeastern University.” Ex. 1004, 232 (Abstract); see Pet. Reply 13. Chiricescu specifically notes “[a]t Northeastern University, the 3-D Microelectronics group has developed a unique technology which allows us to design individual CMOS circuits and stack them to build 3-D layered FPGAs which can have vertical metal 17 Dr. Souri’s declaration testimony cited by Patent Owner (Ex. 2011 ¶ 61) is a single-sentence conclusion that provides no more reasoning than that included in the Patent Owner Response to the Petition (Paper 19).” slip op. at 33
- Obviousness (§103) › Graham factors (scope of art, differences, level of skill)UnpatentableUnpatentable
“3. Independent Claims 1, 2, 26, and 27 Turning to the independent claims 1, 2, 26, and 27, Petitioner presents” slip op. at 47
Patent outcomesUS 7,126,214 unpatentableClaim construction§ 103 obviousnesscites Phillips · KSR · GrahamPatents in suitUS 7,126,214 - Xilinx, Inc. v. Arbor Global Strategies, LLCAll claims unpatentablePTAB · Mar 2, 2022 · IPR2020-01567 · APJ Barbara A Benoit · IPR · Final written decision
The Board held claims 1–6 and 26–31 unpatentable as obvious over the cited combinations of prior art.
RulingsFinal written decision- Skill levelOther
“B. Level of Ordinary Skill in the Art The parties dispute the level of ordinary skill in the art. The level of” slip op. at 9
- Claim Construction › Threshold & procedure › Whether a term needs construction (O2 Micro)Other
“C. Claim Construction In an inter partes review, the Board construes each claim “in” slip op. at 10
- Obviousness (§103) › Motivation to combine / reasonable expectation of successUnpatentableMotivation foundUnpatentable
“reasoning with some rational underpinning to support the legal conclusion of obviousness.” KSR, 550 U.S. at 418. More specifically, Petitioner must demonstrate by a preponderance of evidence that “a skilled artisan would have had reason to combine the teaching of the prior art references to achieve the claimed invention, and that the skilled artisan would have had a reasonable expectation of success from doing so.” PAR Pharm., Inc. v. TWI Pharm., Inc., 773 F.3d 1186, 1193 (Fed. Cir. 2014).” slip op. at 8
- Strike new argumentNew argument consideredDecided for petitioner
“we do not agree with Patent Owner that we should not consider Dr. Franzon’s Reply Declaration. Patent Owner makes only general assertions that seem to be based primarily on multiple paragraphs being identified in a citation, which as discussed below we find provide context for Petitioner’s arguments. Additionally, Patent Owner does not address the significant overlap in the cited paragraphs with arguments made in the Reply. Moreover, in reaching our decision regarding the patentability of the challenged claims, we exercised judgment as to all the evidence cited by the parties for its relevance, context, and substance, and weighed it accordingly.” slip op. at 91
Patent outcomesUS 7,126,214 unpatentableClaim construction§ 103 obviousnesscites Phillips · KSR · GrahamPatents in suitUS 7,126,214 - Samsung Electronics Co., Ltd. / Taiwan Semiconductor Manufacturing Co. Ltd. v. Arbor Global Strategies LLCAll claims unpatentablePTAB · Nov 24, 2021 · IPR2021-00391 · APJ Karl D Easthom · IPR · Final written decision
Claims 1, 3, 5–9, 11, 13–17, 19–22, 25, 26, 28, and 29 are unpatentable as anticipated by Alexander or obvious over the stated prior-art combinations.
RulingsFinal written decision- Skill levelSkill level petitioner adoptedDecided for petitioner
“We adopt Petitioner’s proposed level of ordinary skill in the art as we did in the Institution Decision, which comports with the teachings of the ’035 patent and the asserted prior art. See Inst. Dec. 19. Patent Owner’s proposed level is slightly lower than Petitioner’s but it overlaps with Petitioner’s proposed level. Even if we adopted Patent Owner’s proposed level, the outcome would remain the same. C.” slip op. at 9
- Claim Construction › Threshold & procedure › Whether a term needs construction (O2 Micro)No construction neededNot reached
“accordance with the ordinary and customary meaning of such claim as understood by one of ordinary skill in the art and the prosecution history pertaining to the patent.” 37 C.F.R. § 42.100(b) (2019). Under the same standard applied by district courts, claim terms acquire their plain and ordinary meaning as would have been understood by a person of ordinary skill in the art at the time of the invention and in the context of the entire patent disclosure. Phillips v. AWH Corp., 415 F.3d 1303, 1313 (Fed. Cir. 2005) (en banc). “There are only two exceptions to this general rule: 1) when a patentee sets out a definition and acts as his own lexicographer, or 2) when the patentee disavows the full scope of a claim term either in the specification or during prosecution.” Thorner v. Sony Comput. Entm’t Am. LLC, 669 F.3d 1362, 1365 (Fed. Cir. 2012). Based on the current record, no terms require explicit construction. See, e.g., Nidec Motor Corp. v. Zhongshan Broad Ocean Motor Co., 868 F.3d 1013, 1017 (Fed. Cir. 2017) (“[W]e need only construe terms ‘that are in controversy, and only to the extent necessary to resolve the controversy’. . . .” (quoting Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999))). D.” slip op. at 9
- Expert testimonyPetitioner expert creditedPatent owner expert discountedDecided for petitioner
“does not support Patent Owner’s argument about “undue experimentation” with respect to how to combine the teachings of Koyanagi and Alexander to arrive at the claimed processor module. In the passage containing the quoted testimony that Patent Owner relies upon, Dr. Shanfield testifies as follows: You have obviously got to have a circuit in mind that you're wanting to create a system-level circuit, a module-level circuit; and so you’re going to need to consider which connections you want a TSV connecting to something below. So you don't just slap it together without worrying about what connects to what. On the other hand, the putting together of the -- in Bertin, he describes the putting together of these chips and how that can be done in detail. And that piece of it is -- I guess you could characterize that as something that comes with the process and in itself isn’t something you think specifically about every one of 50,000 connections. They’re all done by the process that he gives an example of. Ex. 2014, 82:4–19.13 Dr. Shanfield’s testimony indicates that artisans of ordinary skill readily would have been able to connect different die circuits together “obviously” with “a circuit in mind . . . to create a system-level circuit, [or] a module-level circuit . . . consider[ing] which [TSV] connections [she] 13 Bertin (Ex. 1009) is employed in the ground discussed below. See infra § II.G. want[s].” See id. As Petitioner similarly argues, “[n]othing in Dr. Shanfield’s testimony, however, suggests that Petitioner ‘slap[ped] together’ Koyanagi and Alexander.” Reply 14; Ex. 1030 ¶ 79 (testifying that Patent Owner quotes his testimony “out of context” and that “at the system or circuit design level, each TSV is an interconnection between specific circuits”).” slip op. at 34
- Novelty / Anticipation (§102) › Anticipation standard (single reference, every element)UnpatentableUnpatentable
“Initially, Alexander, a prior art reference, carries a presumption of enablement. Antor Media, 689 F.3d at 1287–1288; Amgen, 314 F.3d at 1355. Patent Owner argues that the presumption does not apply because “for a non-patent publication, such as Alexander, to be presumptively enabling, it must have been “cited by an examiner . . . barring any showing to the contrary by a patent applicant or patentee.” PO Resp. 13 (quoting Antor Media, 689 F.3d at 1288. Patent Owner also argues that “[w]hile it is true that a ‘[e]nablement of an anticipatory reference may be demonstrated by a later reference,’ the Federal Circuit has made clear that the later reference ‘must show that the claimed subject matter was in possession of the public more than one year prior to the applicant’s filing date.’” Id. at 16 (quoting Bristol-Myers Squibb Co. v. Ben Venue Labs., Inc., 246 F.3d 1368, 1379 (Fed. Cir. 2001)).8 Petitioner argues that Patent Owner “mispresents the law.” As Petitioner argues, ‘[a] prior art printed publication does not need to have been ‘cited by an examiner’ to be presumed enabling.” Reply 5. In Corephotonics, 2021 WL 2577597, at *4 (nonprecedential), in the context of AIA trial proceedings, the court held that “regardless of the forum, prior art patents and publications enjoy a presumption of enablement, and the patentee/applicant has the burden to prove nonenablement for such prior art” and that “[i]t was error for the Board to suggest otherwise.” The 1995 publication date of Alexander antedates the’035 patent’s effective filing date of December 5, 2001 by more than six years. See Ex. 1006, 1 (“0-7803-2702-1/95 $ 4.00 © IEEE-1995”); PO Resp. 4 (specifying “December 5, 2001” as “the earliest effective filing date of the ’035 Patent”); Inst Dec. 20–25 (finding the publication date of Alexander is 8 The “more than one year prior to the applicant’s filing date” requirement arises from “anticipation under 35 U.S.C. § 102(b).” See Bristol-Myers Squibb, 246 F.3d at 1379.” slip op. at 14
Patent outcomesUS RE42,035 unpatentableClaim construction§ 102 anticipation§ 103 obviousnesscites Phillips · KSR · Graham - Samsung Electronics Co., Ltd. / Taiwan Semiconductor Manufacturing Co. Ltd. v. Arbor Global Strategies LLCAll claims unpatentablePTAB · Nov 24, 2021 · IPR2020-01020 · APJ Karl D Easthom · IPR · Final written decision
The Board held claims 1, 5, and 7 anticipated by Alexander, and all challenged claims unpatentable as obvious over the stated combinations.
RulingsFinal written decision- Skill levelSkill level petitioner adoptedDecided for petitioner
“Patent Owner contends that “a person of ordinary skill in the art . . . would have had a Bachelor’s degree in Electrical Engineering or a related and either (1) two or more years of industry experience; and/or (2) an advanced degree in Electrical Engineering or related field.” PO Resp. 4–5 (citing Ex. 2015 ¶ 33). We adopt Petitioner’s proposed level of ordinary skill in the art as we did in the Institution Decision, which comports with the teachings of the ’035 patent and the asserted prior art. See Inst. Dec. 19. Patent Owner’s proposed level is slightly lower than Petitioner’s but it overlaps with Petitioner’s proposed level. Even if we adopted Patent Owner’s proposed level, the outcome would remain the same. C.” slip op. at 8
- Claim Construction › Threshold & procedure › Whether a term needs construction (O2 Micro)No construction neededOther
“accordance with the ordinary and customary meaning of such claim as understood by one of ordinary skill in the art and the prosecution history pertaining to the patent.” 37 C.F.R. § 42.100(b) (2019). Under the same standard applied by district courts, claim terms acquire their plain and ordinary meaning as would have been understood by a person of ordinary skill in the art at the time of the invention and in the context of the entire patent disclosure. Phillips v. AWH Corp., 415 F.3d 1303, 1313 (Fed. Cir. 2005) (en banc). “There are only two exceptions to this general rule: 1) when a patentee sets out a definition and acts as his own lexicographer, or 2) when the patentee disavows the full scope of a claim term either in the specification or during prosecution.” Thorner v. Sony Comput. Entm’t Am. LLC, 669 F.3d 1362, 1365 (Fed. Cir. 2012). Based on the current record, no terms require explicit construction. See, e.g., Nidec Motor Corp. v. Zhongshan Broad Ocean Motor Co., 868 F.3d 1013, 1017 (Fed. Cir. 2017) (“[W]e need only construe terms ‘that are in controversy, and only to the extent necessary to resolve the controversy’. . . .” (quoting Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999))). D.” slip op. at 9
- Novelty / Anticipation (§102) › Anticipation standard (single reference, every element)UnpatentableUnpatentable
“In other words, contrary to Patent Owner’s arguments, Alexander need not enable “wafer-thinning technology,” because challenged claims 1, 5, and 7 at issue here do not require that technology. Even so, the ’035 patent admits the “wafer-thinning technology” was known and “developed by Tru-Sci Technologies” prior to the invention. See Ex. 1001, 2:20–30; Prelim. Resp. 18–19 (citing Ex. 1001, 2:20–30; Ex. 2008); Bristol-Myers Squibb Co. v. Ben Venue Labs., Inc., 246 F.3d 1368, 1379 (Fed. Cir. 2001) (“Enablement of an anticipatory reference may be demonstrated by a later reference”). Accordingly, an artisan of ordinary skill reading Alexander 9 Patent Owner does not challenge this preliminary finding in its Response. After a full review of the record, we incorporate and adopt this finding as supported by a preponderance of the evidence. would have considered Alexander enabled for such known technology at the time of the invention.10” slip op. at 16
- Obviousness (§103) › Motivation to combine / reasonable expectation of successMotivation foundReasonable expectation foundUnpatentable
“Contrary to these arguments, claim 9 does not recite or require a “stacked die hybrid,” “buffer cells,” any improvements in FPGA reconfiguration times, or a “3D IC.” Claim 9 recites a “reconfigurable computer system” in the preamble, but it does not even recite how the “memory” and “processor” functionally or structurally relate to the “first and second integrated circuit die elements” of the “processor module.” As indicated above, Alexander carries a presumption of enablement as a prior art reference. See Antor Media, 689 F.3d at 1288; Amgen, 314 F.3d at 1355. Alexander employs multi-chip module fabrication techniques “to establish electrical contacts between the interconnect substrate and pads on individual dies.” Ex. 1006, 4. As to obviousness, Petitioner relies on known systems that include a microprocessor, FPGA, and memory. Pet. 22–23 (citing “APA Figure 1”). Petitioner persuasively shows that an artisan of ordinary skill readily could have connected the known FPGA module in a processor and memory system as a substitute for a prior art FPGA, with the system performing as predicted, as evidenced by the block diagram wiring connections in admitted prior art Figure 1 of the ’035 patent, in order to save space and increase processing speed with a reasonable expectation of success. See Pet. 10–11, 21–25 (citing Ex. 1002 ¶¶ 85–93). Patent Owner also alleges thermal issues in Alexander render the claimed combination “inoperable.” PO Resp. 25–28. Again, however, Patent Owner relies on a module or stack of a “3D FPGA with other power hungry components, such as logic dies including microprocessors” to support its arguments. Id. at 27. This argument mischaracterizes the breadth of claims 9, 13, and 15, which do not require a stack that includes a 3D FPGA stack with a microprocessor and memory in that stack, as Petitioner shows and as outlined above. Based on the foregoing discussion, Petitioner shows persuasively that” slip op. at 25
Patent outcomesUS RE42,035 unpatentableClaim construction§ 102 anticipation§ 103 obviousnesscites Phillips · KSR · Graham - Samsung Electronics Co., Ltd. / Taiwan Semiconductor Manufacturing Co. Ltd. v. Arbor Global Strategies LLCAll claims unpatentablePTAB · Nov 24, 2021 · IPR2021-00394 · APJ Karl D Easthom · IPR · Final written decision
Claims 1, 4, 5, 8, 10, and 13–15 are unpatentable as obvious over Koyanagi and Alexander, and independently over Bertin and Cooke.
RulingsFinal written decision- Skill levelSkill level petitioner adoptedDecided for petitioner
“Level of Ordinary Skill in the Art Relying on the testimony of Dr. Shanfield, Petitioner contends that [a] person of ordinary skill in the art (“POSITA”) at the time of the alleged invention would have been a person having a Master’s degree in Electrical Engineering, Computer Engineering, or Physics with three to five years of industry experience in integrated circuit design, layout, packaging or fabrication. Ex. 1002 ¶¶ 55–58. A greater level of experience in the relevant field may compensate for less education, and vice versa. Pet. 10.” slip op. at 7
- Claim Construction › Intrinsic evidence (Phillips canons) › Plain and ordinary meaning to a POSITATerm construed patent owner constructionDecided for patent owner
“the Board’s preliminary construction only adds ambiguity to the meaning of this term because it requires “a number of vertical contacts that . . . provide contacts on the surface of the memory die,” and further, claim 1 already recites that “‘a second integrated circuit functional element’ has ‘a number of contact points distributed throughout the surfaces of said functional element.’” See id. at 9 (emphasis added). Therefore, Patent Owner offers the following “suggest[ion]”: “To the extent that the Board finds it necessary to mention contacts in the context of the claimed ‘memory array,’ Patent Owner suggests that the Board use the term ‘a number of vertical contacts distributed throughout the surface of and traversing the memory die.’” PO Resp. 8 (emphasis added). For reasons discussed further below and in the Institution Decision, the record, including the specification, supports Patent Owner’s suggestion, and we determine that Patent Owner’s claim construction suggestion is materially the same as the preliminary claim construction set forth in the Institution Decision. See, e.g., Ex. 1001, 2:41–44 (“[S]ince these differing die do not require wire bonding to interconnect, it is now also possible to place interconnect pads throughout the total area of the various die rather than just around their periphery.”) (emphasis added); Inst. Dec. 24–25. In addition to Patent Owner’s suggestion above, Patent Owner also argues that “the term ‘a memory array functional to accelerate external memory references to the processing element’ means ‘a memory array that allows the parallel loading of data through buffer cells.’” PO Resp. 6 (emphasis added). Patent Owner asserts that “[i]n its preliminary response, Patent Owner advocated that this term should be accorded its plain and ordinary meaning.” PO Resp. 5. It is not clear if Patent Owner maintains (i.e., in its Response) that the phrase carries its plain and ordinary meaning.9 In any event, the record does not support Patent Owner’s proposed requirement for “buffer cells” under the plain and ordinary meaning of the “functional to accelerate” clause or under lexicography principles, prosecution history or otherwise, for the reasons advanced by Petitioner and as addressed below. In line with Patent Owner’s suggestion and as we similarly determined in the Institution Decision, the “functional to accelerate” limitations require “a number of vertical contacts distributed throughout the surface of and traversing the memory die in a vertical direction (vias) to allow multiple short paths for data transfer between the memory and processor.” See Ex. 1001, Fig. 4 (showing numerous contact points); Inst. Dec. 25 (materially similar construction); PO Resp. 8 (Patent Owner’s suggestion). We adopt and incorporate the claim construction findings in the Institution Decision, much of which we repeat here for completeness. See Inst. Dec. 19–25. slip op. at 10
- Obviousness (§103) › Graham factors (scope of art, differences, level of skill)UnpatentableUnpatentable
“As Petitioner argues, the combined Koyanagi and Alexander system mimics the ’951 patent’s disclosure by employing stacked dies with a “large number of contact points distributed throughout the surfaces of the dies.” Pet. 29; see also supra notes 14, 16. Petitioner also provides evidence that an artisan of ordinary skill would have known of several advantages in stacking 3D chips with multiple vias including “high packing density,” “high speed,” “parallel signal processing,” and “integration of many functions on a single chip.” Id. at 4 (citing Ex. 1010, 1704; Ex. 1002 ¶ 39). Petitioner points to Koyanagi’s “key benefit” as “enab[ling]large data bandwidth in vertical data transfers” (Ex. 1007, 17) to mitigate bus bottlenecks, further showing that multiple vias provide for parallel signal processing and increased processing speed in stacked dies as found above. See Pet. 30 (citing Ex. 1007, 17, 19); supra § II.C (Claim Construction); supra notes 14, 16. In other words, Petitioner shows how the combined teachings of Koyanagi and Alexander teach or suggest to an artisan of ordinary skill the accelerate clause in the challenged claims by providing a large number of short parallel via connections, thereby functionally enabling large data bandwidths and parallel processing, as was well-known at the time of the invention. See Pet. 4, 17–23, 28–29; Ex. 1007, 17–18; supra notes 14, 16; Reply 15–17; In re Graves, 69, F.3d 1147, 1152 (Fed. Cir. 1995)(holding that “Rockwell . . . anticipates claim 4, even if it does not specifically disclose simultaneous monitoring of the output points, if simultaneous or parallel monitoring is within the knowledge of a skilled artisan”).” slip op. at 35
- Obviousness (§103) › Motivation to combine / reasonable expectation of successMotivation foundReasonable expectation foundDecided for petitioner
“As Petitioner also argues and as summarized above, the Petition “provide[s] a detailed explanation of how Koyanagi and Alexander would have been combined to disclose each limitation of the Challenged Claims and why a POSITA would have been motivated to combine them––‘to create a 3D reconfigurable processor module with improved performance and areaefficiency.’” Reply 16 (quoting Pet. 17). By way of example, Petitioner’s annotated Figure 1M, which represents combined teachings of Koyanagi and Alexander, shows how to connect the dies together using conductive vias as challenged claim 1 requires. Petitioner also provides persuasive detail with respect to the remaining challenged claims at issue in this section (i.e., claims 4, 5, 8, 10, 13–15). See Pet. 31–46. By teaching similar stacking techniques for similar circuits including the use of conductive vias with logic dies including FPGAs, memory, and microprocessors, Koyanagi and Alexander collectively evidence a reasonable expectation of success without undue experimentation in arriving at the claimed invention. See Otsuka Pharm. Co., v. Sandoz, Inc., 678 F.3d 1280, 1296 (Fed. Cir. 2012) (“The inventor's own path itself never leads to a conclusion of obviousness; that is hindsight. What matters is the path that the person of ordinary skill in the art would have followed, as evidenced by the pertinent prior art.”). In other words, Petitioner shows that the claimed invention involves a routine combination of familiar elements to yield predictable results, namely combining Alexander’s known 2D-FPGA die with Koyanagi’s similar die stack, or simply substituting Alexander’s known 2D-FPGA die in place of a similar DRAM memory die in the die stack of Koyanagi, with the coupled circuits functioning with processing speed gains and other benefits as expected. See Pet. 27–29; Reply 14 (citing KSR, 550 U.S. at 416 (“The combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results.”)).” slip op. at 42
Patent outcomesUS 7,282,951 unpatentableClaim construction§ 103 obviousnesscites Phillips · KSR · GrahamPatents in suitUS 7,282,951 - Samsung Electronics Co., Ltd. / Taiwan Semiconductor Manufacturing Co. Ltd. v. Arbor Global Strategies LLCAll claims unpatentablePTAB · Nov 24, 2021 · IPR2020-01021 · APJ Karl D Easthom · IPR · Final written decision
Claims 1, 4, 5, 8, 10, and 13–15 are unpatentable as obvious over Koyanagi and Alexander, and independently over Bertin and Cooke.
RulingsFinal written decision- Skill levelSkill level petitioner adoptedDecided for petitioner
“Level of Ordinary Skill in the Art Relying on the testimony of Dr. Shanfield, Petitioner contends that [a] person of ordinary skill in the art (“POSITA”) at the time of the alleged invention would have been a person having a Master’s degree in Electrical Engineering, Computer Engineering, or Physics with three to five years of industry experience in integrated circuit design, layout, packaging or fabrication. Ex. 1002 ¶¶ 55–58. A greater level of experience in the relevant field may compensate for less education, and vice versa.” slip op. at 7
- Claim Construction › Intrinsic evidence (Phillips canons) › Plain and ordinary meaning to a POSITATerm construed patent owner constructionDecided for patent owner
“the Board’s preliminary construction only adds ambiguity to the meaning of this term because it requires “a number of vertical contacts that . . . provide contacts on the surface of the memory die,” and further, claim 1 already recites that “‘a second integrated circuit functional element’ has ‘a number of contact points distributed throughout the surfaces of said functional element.’” See id. at 9 (emphasis added). Therefore, Patent Owner offers the following “suggest[ion]”: “To the extent that the Board finds it necessary to mention contacts in the context of the claimed ‘memory array,’ Patent Owner suggests that the Board use the term ‘a number of vertical contacts distributed throughout the surface of and traversing the memory die.’” PO Resp. 8 (emphasis added). For reasons discussed further below and in the Institution Decision, the record, including the specification, supports Patent Owner’s suggestion, and we determine that Patent Owner’s claim construction suggestion is materially the same as the preliminary claim construction set forth in the Institution Decision. See, e.g., Ex. 1001, 2:41–44 (“[S]ince these differing die do not require wire bonding to interconnect, it is now also possible to place interconnect pads throughout the total area of the various die rather than just around their periphery.”) (emphasis added); Inst. Dec. 24–25. slip op. at 10
- Obviousness (§103) › Motivation to combine / reasonable expectation of successMotivation foundReasonable expectation foundUnpatentable
“These claim construction arguments that rely on “buffer cells” fail for the reasons noted above, the challenged claims do not require buffer cells. See supra § II.C (Claim Construction). As summarized above, the ’951 patent describes in its abstract and other places, including in reference to Figure 4, providing accelerated data transfers and reconfiguration without buffer cells by using numerous short vias to connect circuits in the stacked dies. See id. As outlined above, Petitioner provides ample motivation supported by the record as to “how and why” an artisan of ordinary skill would have combined the stacked die features of Koyanagi with the similar features of Alexander, to include the well-known FGPA, and it shows how the vertical interconnections employed in both references track the disclosed invention to obtain the claimed acceleration. See, e.g., Pet. 29 (annotating Koyanagi’s Figure 1). Wiring similar well-known circuits with short conductive vias instead of long conventional conductors would have been obvious and well-within the ordinary skill of an artisan, motivated by many reasons (for example, speed/bandwidth gains, compactness, power consumption, FPGA design flexibility) as the Petition shows and as Koyanagi and Alexander suggest as discussed above. See, e.g., Ex. 1006, Abstract (describing a “fabrication technology” and “expected manufacturing yield”), 1 (describing “10,000 solder bumps” “to establish the vertical interconnections” and “enabling electrical interconnections between the two sides of the die,” by “adapting multi-chip module (MCM) fabrication technology”); Ex. 1007, 17 (similarly describing MCM technology and using 10,000 (105) “interconnections per chip” to make 3D MCMs “fabricated using our new integration technology”), Fig. 6 (showing “Fabrication sequence of 3D LSI”).” slip op. at 37
- Obviousness (§103) › Motivation to combine / reasonable expectation of success › Teaching awayTeaching away not foundDecided for petitioner
“However, as Petitioner argues and as Dr. Chakrabarty confirms, using many short vertical conductive vias (e.g., TSVs) versus long conductive runs “reduces power consumption and improves heat removal (because TSVs also serve as heat pipes).” Reply 17 (citing Ex. 1007, 17). In other words, Dr. Chakrabarty acknowledges that [w]hat Koyanagi says is actually obvious to anybody who is skilled in the art. Anybody who is skilled in the art would know that via is conductive. It is a conductor for both electricity and for heat. And therefore, if you have lots of vias, you’re going to take out the heat. Ex. 1035, 256:9–15 (emphasis added); see Reply 17 (partially quoting Ex. 1035, 256:9–15). Therefore, as Petitioner persuasively argues, rather than ignoring thermal issues or deterring a person of skill in the art from combining Koyanagi and Alexander, “a POSITA would have been motivated to find a solution to the alleged thermal issues, and would have recognized that a large number of 3D interconnections between dies contribute to such a solution.” See Reply 21 (citing Ex. 1030 ¶ 53).” slip op. at 50
Patent outcomesUS 7,282,951 unpatentableClaim construction§ 103 obviousnesscites Phillips · KSR · GrahamPatents in suitUS 7,282,951 - Samsung Electronics Co., Ltd. / Taiwan Semiconductor Manufacturing Co. Ltd. v. Arbor Global Strategies LLCAll claims unpatentablePTAB · Nov 24, 2021 · IPR2021-00393 · APJ Sharon Fenick · IPR · Final written decision
Claims 13, 14, 16–23, and 25–30 are unpatentable as obvious over Koyanagi and Cooke and over Bertin and Cooke.
RulingsFinal written decision- Skill levelSkill level petitioner adoptedDecided for petitioner
“Level of Ordinary Skill in the Art Relying on the testimony of Dr. Shanfield, Petitioner contends that [a] person of ordinary skill in the art (“POSITA”) at the time of the ’226 Patent would have been a person having a Master’s degree in Electrical Engineering, Computer Engineering, or Physics with three to five years of industry experience in integrated circuit design, layout, packaging or fabrication. Ex. 1002 ¶¶ 45–48. A greater level of experience in the relevant field may compensate for less education, and vice versa.” slip op. at 7
- Claim Construction › Functional claiming / §112(f) means-plus-function › Whether §112(f) applies (Williamson, nonce words)§112(f) appliesDecided for petitioner
“13.4 in claim 13) and “means for updating the plurality of configuration logic cells within one clock cycle” (limitation 22.4 in claim 22) are means-plus-function limitations and should be construed as per 35 U.S.C. § 112, ¶ 6. Pet. 9; PO Resp. 6–7. Both of these limitations listed above recite “means” and further recite a function, thus creating a presumption that 35 U.S.C. § 112, ¶ 6 applies. See 35 U.S.C. § 112, ¶ 6 (“An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.”); see also Williamson v. Citrix Online, LLC, 792 F.3d 1339, 1349 (Fed. Cir. 2015) (en banc in relevant part) (quoting Personalized Media Commc’ns, LLC v. Int’l Trade Comm’n, 161 F.3d 696, 703 (Fed. Cir. 1998)) (holding that “use of the word ‘means’ creates a presumption that § 112, ¶ 6 applies”). We agree with the parties that these limitations are means-plus-function limitations subject to 35 U.S.C. § 112, ¶ 6.” slip op. at 9
- Claim Construction › Intrinsic evidence (Phillips canons) › Plain and ordinary meaning to a POSITATerm construed board ownDecided for petitioner
“Patent Owner, in focusing on this portion of the ’226 patent disclosure, does not adequately explain why buffer cells and configuration memory cells must be included in the proper construction of “wide configuration data port,” and seeks to import a functional description of the use of a wide configuration data port (“that allows parallel updating of logic cells in a programmable array through use of buffer cells”) into the claim construction. PO Resp. 11–14; PO Sur-reply 2–4. While the discussion in the ’226 patent describes an example of a wide configuration data port used in a specific way that aligns with Patent Owner’s proposal (Ex. 1001, 4:45– 59), other examples of the use of a wide configuration data port are included (id. at 4:59–65), and therefore we do not agree that one of ordinary skill would understand this use to be part of the construction of the term. We agree with Petitioner that the proper construction of the term does not require buffer cells to be specifically described. See Pet. Reply 6–9. Rather, we note that the specification of the ’226 patent contrasts loading of data to an FPGA in a byte serial fashion through a narrow port, which “results in [] long reconfiguration times,” with the use of a wide configuration data port, and therefore we determine that one of ordinary skill would understand the wide configuration data port, in contrast to the byte serial “relatively narrow” port, to include parallel connections between cells in the dies. See Ex. 1001, 4:3–9. This additionally is consistent with certain arguments by Patent Owner, for example in the Patent Owner’s Response, which opens with a discussion of the “inventive” processor’s arrangement of die-area contacts, such as through-silicon vias, “into a wide configuration data port” and we find that description more consistent with the proper construction of this term. PO Resp. 1–2; see also id. at 8 (“[T]he ’226 Patent specifically identifies that the wide configuration data port reconfigures both a programmable array and/or logic cells in one clock cycle because it can communicate with many cells (which form an ‘array’) in parallel, and is therefore considered ‘wide.’”)” slip op. at 14
- Claim Construction › Functional claiming / §112(f) means-plus-function › Corresponding structure / algorithm (indefinite if none)Term construed board ownDecided for petitioner
“While corresponding structure need not include all things necessary to enable the claimed invention to work, it must include all structure that actually performs the recited function.” Default Proof Credit Card Sys. Inc. v. Home Depot U.S.A., Inc., 412 F.3d 1291, 1298 (Fed. Cir. 2005). Conversely, structural features that do not actually perform the recited function do not constitute corresponding structure and thus do not serve as claim limitations. Chiuminatta Concrete Concepts, Inc. v. Cardinal Indus., Inc., 145 F.3d 1303, 1308–09, (Fed. Cir. 1998); see B. Braun Med., Inc. v. Abbott Labs., 124 F.3d 1419, 1424 (Fed. Cir. 1997) (“[S]tructure disclosed in the specification is ‘corresponding’ structure only if the specification or prosecution history clearly links or associates that structure to the function recited in the claim.”). Given our construction of wide configuration data port, Patent Owner’s argument that the corresponding structure for this limitation must require that buffer cells on one die element are connected in parallel to cells on another die element is based on the description of the use of buffer cells as used in the updating of the FPGA while it is in operation. PO Supp. Br. 3 (citing Ex. 1001, 4:50–54, Fig. 5). However, we note that this description is followed by the disclosure that “[t]he buffer cells 88 are preferably a portion of the memory die 66.” Ex. 1001, 4:50–54. It does not appear, therefore, that buffer cells are always a portion of the memory die, or are required when the FPGA is not in operation, and thus we decline to require in the corresponding structure that they be specified to be on a specific separate die element. Rather, we find that what is disclosed as actually performing the recited function of “reconfiguring the programmable array within one clock cycle” is “a wide configuration data port and contact points formed throughout the area of the first integrated circuit die element and another integrated circuit die element.” The support for this is found in the ’266 patent’s comparison of the long reconfiguration times through a narrow port (Ex. 1001, 4:3–9) with the time to reconfigure through a wide configuration data port with a significantly increased number of connections (id. at 4:45– 65), and the implementation of this in a module that has multiple dies “which have a number of corresponding contact points, or holes, 70 formed throughout the area of the [die] package” (id. at 4:9–20). The use of a wide configuration data port, as per our construction, implicates two die elements. This was reflected in our preliminary claim construction, for which the corresponding structure described “contact points distributed through the slip op. at 18
Patent outcomesUS 6,781,226 unpatentableClaim construction§ 103 obviousnesscites Phillips · KSR · GrahamPatents in suitUS 6,781,226 - Samsung Electronics Co., Ltd. / Taiwan Semiconductor Manufacturing Co. Ltd. v. Arbor Global Strategies LLCAll claims unpatentablePTAB · Nov 24, 2021 · IPR2020-01022 · APJ Sharon Fenick · IPR · Final written decision
Claims 13, 14, 16–23, and 25–30 are unpatentable as obvious over Koyanagi and Cooke, and over Bertin and Cooke.
RulingsFinal written decision- Skill levelSkill level petitioner adoptedDecided for petitioner
“Level of Ordinary Skill in the Art Relying on the testimony of Dr. Shanfield, Petitioner contends that [a] person of ordinary skill in the art (“POSITA”) at the time of the ’226 Patent would have been a person having a Master’s degree in Electrical Engineering, Computer Engineering, or Physics with three to five years of industry experience in integrated circuit design, layout, packaging or fabrication. Ex. 1002 ¶¶ 45–48. A greater level of experience in the relevant field may compensate for less education, and vice versa. Pet. 7–8. Patent Owner asserts that [a] person of ordinary skill in the art (“POSITA”) around December 5, 2001 (the earliest effective filing date of the ’226 6 No argument or evidence regarding secondary considerations has been presented in this proceeding. Patent) would have had a Bachelor’s degree in Electrical Engineering or a related field, and either (1) two or more years of industry experience; and/or (2) an advanced degree in Electrical Engineering or related field. PO Resp. 5–6 (citing Ex. 2009 ¶¶ 31–34). As we did in the Decision on Institution, we adopt Petitioner’s proposed level of ordinary skill in the art, which comports with the teachings of the ’226 patent and the asserted prior art. See Dec. on Inst. 18–19. Patent Owner’s proposed level is lower but it overlaps with Petitioner’s proposed level. Even if we adopted Patent Owner’s proposed level, the outcome would remain the same. C.” slip op. at 7
- Claim Construction › Functional claiming / §112(f) means-plus-function › Whether §112(f) applies (Williamson, nonce words)§112(f) appliesDecided for petitioner
“Both of these limitations listed above recite “means” and further recite a function, thus creating a presumption that 35 U.S.C. § 112, ¶ 6 applies. See 35 U.S.C. § 112, ¶ 6 (“An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.”); see also Williamson v. Citrix Online, LLC, 792 F.3d 1339, 1349 (Fed. Cir. 2015) (en banc in relevant part) (quoting Personalized Media Commc’ns, LLC v. Int’l Trade Comm’n, 161 F.3d 696, 703 (Fed. Cir. 1998)) (holding that “use of the word ‘means’ creates a presumption that § 112, ¶ 6 applies”). We agree with the parties that these limitations are means-plus-function limitations subject to 35 U.S.C. § 112, ¶ 6.” slip op. at 9
- Claim Construction › Intrinsic evidence (Phillips canons) › Plain and ordinary meaning to a POSITATerm construed board ownDecided for petitioner
“Patent Owner, in focusing on this portion of the ’226 patent disclosure, does not adequately explain why buffer cells and configuration memory cells must be included in the proper construction of “wide configuration data port,” and seeks to import a functional description of the use of a wide configuration data port (“that allows parallel updating of logic cells in a programmable array through use of buffer cells”) into the claim construction. PO Resp. 11–14; PO Sur-reply 2–4. While the discussion in the ’226 patent describes an example of a wide configuration data port used in a specific way that aligns with Patent Owner’s proposal (Ex. 1001, 4:45– 59), other examples of the use of a wide configuration data port are included (id. at 4:59–65), and therefore we do not agree that one of ordinary skill would understand this use to be part of the construction of the term. We agree with Petitioner that the proper construction of the term does not require buffer cells to be specifically described. See Pet. Reply 6–9. Rather, we note that the specification of the ’226 patent contrasts loading of data to an FPGA in a byte serial fashion through a narrow port, which “results in [] long reconfiguration times,” with the use of a wide configuration data port, and therefore we determine that one of ordinary skill would understand the wide configuration data port, in contrast to the byte serial “relatively narrow” port, to include parallel connections between cells in the dies. See Ex. 1001, 4:3–9. This additionally is consistent with certain arguments by Patent Owner, for example in the Patent Owner’s Response, which opens with a discussion of the “inventive” processor’s arrangement of die-area contacts, such as through-silicon vias, “into a wide configuration data port” and we find that description more consistent with the proper construction of this term. PO Resp. 1–2; see also id. at 8 (“[T]he ’226 Patent specifically identifies that the wide configuration data port reconfigures both a programmable array and/or logic cells in one clock cycle because it can communicate with many cells (which form an ‘array’) in parallel, and is therefore considered ‘wide.’”)” slip op. at 14
- Claim Construction › Functional claiming / §112(f) means-plus-function › Corresponding structure / algorithm (indefinite if none)Term construed board ownDecided for petitioner
“While corresponding structure need not include all things necessary to enable the claimed invention to work, it must include all structure that actually performs the recited function.” Default Proof Credit Card Sys. Inc. v. Home Depot U.S.A., Inc., 412 F.3d 1291, 1298 (Fed. Cir. 2005). Conversely, structural features that do not actually perform the recited function do not constitute corresponding structure and thus do not serve as claim limitations. Chiuminatta Concrete Concepts, Inc. v. Cardinal Indus., Inc., 145 F.3d 1303, 1308–09, (Fed. Cir. 1998); see B. Braun Med., Inc. v. Abbott Labs., 124 F.3d 1419, 1424 (Fed. Cir. 1997) (“[S]tructure disclosed in the specification is ‘corresponding’ structure only if the specification or prosecution history clearly links or associates that structure to the function recited in the claim.”). Given our construction of wide configuration data port, Patent Owner’s argument that the corresponding structure for this limitation must require that buffer cells on one die element are connected in parallel to cells on another die element is based on the description of the use of buffer cells as used in the updating of the FPGA while it is in operation. PO Supp. Br. 3 (citing Ex. 1001, 4:50–54, Fig. 5). However, we note that this description is followed by the disclosure that “[t]he buffer cells 88 are preferably a portion of the memory die 66.” Ex. 1001, 4:50–54. It does not appear, therefore, that buffer cells are always a portion of the memory die, or are required when the FPGA is not in operation, and thus we decline to require in the corresponding structure that they be specified to be on a specific separate die element. Rather, we find that what is disclosed as actually performing the recited function of “reconfiguring the programmable array within one clock cycle” is “a wide configuration data port and contact points formed throughout the area of the first integrated circuit die element and another integrated circuit die element.” The support for this is found in the ’266 patent’s comparison of the long reconfiguration times through a narrow port (Ex. 1001, 4:3–9) with the time to reconfigure through a wide configuration data port with a significantly increased number of connections (id. at 4:45– 65), and the implementation of this in a module that has multiple dies “which have a number of corresponding contact points, or holes, 70 formed throughout the area of the [die] package” (id. at 4:9–20). The use of a wide configuration data port, as per our construction, implicates two die elements. This was reflected in our preliminary claim construction, for which the corresponding structure described “contact points distributed through the slip op. at 18
Patent outcomesUS 6,781,226 unpatentableClaim construction§ 103 obviousnesscites Phillips · KSR · GrahamPatents in suitUS 6,781,226
Holdings, summaries, rulings, issues, outcomes, winners and claim constructions shown for a decision were generated by a large language model reading the opinion. They are a guide to the decision, not the decision. Confirm every one against the court's own text before relying on it. Outcomes read from the patent owner’s side. Party names are extracted from the decision and are missing on about 900 short Director denials and scans, which carry the trial number instead.