- Samsung Electronics Co., Ltd / Dell Technologies Inc. et al. v. Mypaq Holdings Ltd.All claims unpatentablePTAB · May 17, 2023 · IPR2022-01131 · APJ Daniel J Galligan · IPR · Final written decision
Claims 1–20 are unpatentable: Chagny anticipates claims 1, 2, 4–6, 11, 14–16, and 20; Hirst anticipates claims 1, 6–10, and 16–18; other grounds also establish unpatentability.
RulingsFinal written decision- Skill levelSkill level board ownDecided for patent owner
“We agree with Patent Owner that some degree of familiarity with power electronics would be necessary for a POSITA given the subject matter at issue, and we understood this to be implicit in part (i) of Petitioner’s definition. To address Patent Owner’s concern, we clarify that a person with a Master of Science in Electrical Engineering or an equivalent field would need experience in power electronics to qualify as a POSITA. We are reluctant to use Patent Owner’s formulation of “some independent expertise in power electronics” (PO Resp. 17–18 (emphasis added)) because it could be read to include an expert level of skill rather than an ordinary level of skill. Thus, we determine that a POSITA would have had either (i) a Master of Science in Electrical Engineering, or an equivalent field, and experience in power electronics or (ii) a Bachelor of Science in Electrical Engineering or an equivalent field as well as two years of experience in the design of power electronics.” slip op. at 7
- Claim Construction › Intrinsic evidence (Phillips canons) › Plain and ordinary meaning to a POSITATerm construed petitioner constructionDecided for petitioner
“We do not agree with Patent Owner’s interpretation of the term “system operational state of said load.” As an initial matter, Patent Owner does not direct us to, and we do not find, a definition of “system operational state” of a load in the ’759 patent. As noted above, Patent Owner’s proposed definition is that “the term ‘system operational state’ as it pertains to engineering systems, refers to the way in which the system as a whole is being employed or utilized.” PO Resp. 18–19 (citing Ex. 2018 ¶ 51). Claims 1, 6, and 16, however, recite “a system operational state of [a/said] load” (emphasis added), not the system as a whole. Patent Owner’s proposed construction, therefore, is not consistent with the claim language. Patent Owner points to examples disclosed in the ’759 patent in an attempt to narrow the meaning of the claim term and, as further discussed below, to distinguish the prior art. See PO Resp. 19–20 (“The ’759 Patent provides examples of signals indicating system operational states including signals . . . .” (citing Ex. 1001, 7:17–28)); see also PO Resp. 46–47 (similar argument citing Ex. 1001, 7:16–28). But the ’759 patent states that these are non-limiting examples. Ex. 1001, 7:16–17 (“Further examples indicating a system operational state include, without limitation . . . .”).” slip op. at 9
- Novelty / Anticipation (§102) › Anticipation standard (single reference, every element)UnpatentableUnpatentable
“ordinary skill in the art is immaterial because Petitioner’s ground is anticipation (PO Sur-reply 12), we understand that Petitioner is relying on what a person of ordinary skill in the art would have understood from Chagny’s disclosure. See Pet. 43–45, 48–49. This is appropriate and indeed necessary because “[a]nticipation is established when ‘one skilled in the art would reasonably understand or infer from the prior art reference’s teaching that every claim [limitation] was disclosed in that single reference.’” CRFD Research, Inc. v. Matal, 876 F.3d 1330, 1338 (Fed. Cir. 2017) (quoting Akamai Techs., Inc. v. Cable & Wireless Internet Servs., Inc., 344 F.3d 1186, 1192–93 (Fed. Cir. 2003)). We also credit Dr. Kiaei’s unrebutted testimony that, “for a buck power converter, the output voltage is equal to the input voltage times the duty cycle of the high-side switch (referred to as charge switch [220] in Chagny).” Ex. 1002 ¶ 134. As noted above, Chagny discloses that “controller module 210 receives the regulated DC voltage output 295 as a feedback input for regulating the output of the VRM 200.” Ex. 1004, 4:63–65, cited in Pet. 48. Thus, we find that Chagny discloses controlling the duty cycle as a function of the output voltage in order to regulate the output voltage as part of the feedback loop. As to Patent Owner’s argument that “Chagny does not discuss how the conduction period is determined or what the duty cycle is” (PO Sur-reply 13), claim 1 does not recite any particular value for the duty cycle, and Patent Owner does not dispute Petitioner’s arguments and Dr. Kiaei’s voltage, as discussed in the previous paragraph. As for Patent Owner’s argument regarding controlling the duty cycle “in accordance with said command,” Petitioner’s contention is that charge and discharge control signals 212 and 214 have the switching frequency 216 that is selected based on activity input 202 and, therefore, that Chagny discloses controlling the duty cycle “in accordance with” activity input 202 based on the relationship between frequency and period of the duty cycle. Pet. 49 (citing Ex. 1004, 4:66–5:2, 5:28–31, 5:34–46); Pet. Reply 19–20 (citing Ex. 1026 ¶ 24). The switching frequency is the inverse of the switching period. Ex. 1026 ¶ 24. We credit Dr. Kiaei’s unrebutted testimony that, “[a]s a matter of simple math, the duty cycle can therefore also be described as a function of both the conduction period and the switching frequency.” Ex. 1026 ¶ 24. By disclosing setting the switching frequency and, thus, the switching period, Chagny discloses that the duty cycle is controlled “in accordance with” activity input 202, upon which the switching frequency is based. Based on Petitioner’s contentions and evidence and for the reasons discussed above, we find that Chagny discloses controlling the duty cycle of charge switch 220 as a function of the feedback from the regulated DC voltage output 295 based on Chagny’s disclosure that “controller module 210 receives the regulated DC voltage output 295 as a feedback input for regulating the output of the VRM 200.” Ex. 1004, 4:63–65. We also find that Chagny discloses controlling the duty cycle of charge switch 220 in accordance with the command to enter a power converter operational state based on Chagny’s disclosure that frequency selector module 215 receives activity input 202 and selects switching frequency 216 to match the activity” slip op. at 25
- Obviousness (§103) › Motivation to combine / reasonable expectation of successUnpatentableMotivation foundUnpatentable
“Petitioner argues that combining “Chagny’s system to further include the control functions of Clark along with the ‘control word’ and ‘Vstable’ signals that Clark uses to communicate between the microprocessor and the power converter” “represents the use of a known technique (i.e., Clark’s dynamic control of the power converter output voltage) to improve a similar device (i.e., Chagny’s information handling system and voltage regulator module) in the same way.” Pet. 61 (citing Ex. 1005, 3:44–60, 5:24–36; Ex. 1002 ¶¶ 189–190). Petitioner argues that a person of ordinary skill in the art would have had a reasonable expectation of success in combining these teachings because “Chagny is already configured to send control signals to its power converter based on the activity level of its processor.” Pet. 61 (citing Ex. 1004, 4:40–43, 5:9–12, Fig. 2A; Ex. 1002 ¶ 190). For claims 3, 12, and 19, Petitioner argues that Clark’s Vstable signal indicates the power converter status because it informs core logic 50 whether voltage regulator 40 has transitioned from one voltage to another. Pet. 62– 63 (citing Ex. 1005, 5:24–36, Fig. 2). For claim 13, Petitioner argues that the Vstable signal indicates that voltage regulator 40 is stable and, therefore, “fully operational.” Pet. 64 (citing Ex. 1005, 5:27–36; Ex. 1002 ¶ 197). Petitioner’s contentions and evidence, summarized above, are persuasive. Based on those contentions, we find that the combination of Chagny and Clark teaches the subject matter of claims 3, 12, 13, and 19 and that the “combination represents the use of a known technique (i.e., Clark’s dynamic control of the power converter output voltage) to improve a similar” slip op. at 35
Patent outcomesUS 7,675,759 unpatentableClaim construction§ 102 anticipation§ 103 obviousnesscites KSRPatents in suitUS 7,675,759 - Samsung Electronics Co., Ltd / Dell Technologies Inc. et al. v. Mypaq Holdings Ltd.All claims unpatentablePTAB · May 17, 2023 · IPR2022-00312 · APJ Daniel J Galligan · IPR · Final written decision
Claims 1–20 are unpatentable: claims 1–20 under Hirst and Chagny grounds, and claims 3, 12, 13, and 19 also under Chagny and Clark.
RulingsFinal written decision- PTAB / AIA Trials › Institution threshold (reasonable likelihood / more likely than not)InstitutedInstituted
“20 Pet. 10. Patent Owner filed a Preliminary Response. Paper 7. With our authorization, Samsung and Dell filed a reply to the Preliminary Response (Paper 9) addressing discretionary denial issues, and Patent Owner filed a sur-reply (Paper 10). We instituted trial on the asserted grounds of unpatentability. Paper 11 (“Inst. Dec.”) at 30.” slip op. at 3
- PTAB / AIA Trials › Joinder §315(c) / SAS all-or-nothingJoinder, grantedGranted
“After institution, Anker filed a motion for joinder and a petition in IPR2022-01131. We joined Anker as a petitioner in this proceeding. Paper 18.” slip op. at 3
- Skill levelSkill level board ownDecided for patent owner
“We agree with Patent Owner that some degree of familiarity with power electronics would be necessary for a POSITA given the subject matter at issue, and we understood this to be implicit in part (i) of Petitioner’s definition. To address Patent Owner’s concern, we clarify that a person with a Master of Science in Electrical Engineering or an equivalent field would need experience in power electronics to qualify as a POSITA. We are reluctant to use Patent Owner’s formulation of “some independent expertise in power electronics” (PO Resp. 17–18 (emphasis added)) because it could be read to include an expert level of skill rather than an ordinary level of skill. Thus, we determine that a POSITA would have had either (i) a Master of Science in Electrical Engineering, or an equivalent field, and experience in power electronics or (ii) a Bachelor of Science in Electrical Engineering or an equivalent field as well as two years of experience in the design of power electronics.” slip op. at 7
- Claim Construction › Intrinsic evidence (Phillips canons) › Plain and ordinary meaning to a POSITATerm construed board ownNo construction neededDecided for petitioner
“We do not agree with Patent Owner’s interpretation of the term “system operational state of said load.” As an initial matter, Patent Owner does not direct us to, and we do not find, a definition of “system operational state” of a load in the ’759 patent. As noted above, Patent Owner’s proposed definition is that “the term ‘system operational state’ as it pertains to engineering systems, refers to the way in which the system as a whole is being employed or utilized.” PO Resp. 18–19 (citing Ex. 2018 ¶ 51). Claims 1, 6, and 16, however, recite “a system operational state of [a/said] load” (emphasis added), not the system as a whole. Patent Owner’s proposed construction, therefore, is not consistent with the claim language. Patent Owner points to examples disclosed in the ’759 patent in an attempt to narrow the meaning of the claim term and, as further discussed below, to distinguish the prior art. See PO Resp. 19–20 (“The ’759 Patent provides examples of signals indicating system operational states including signals . . . .” (citing Ex. 1001, 7:17–28)); see also PO Resp. 46–47 (similar argument citing Ex. 1001, 7:16–28). But the ’759 patent states that these are non-limiting examples. Ex. 1001, 7:16–17 (“Further examples indicating a system operational state include, without limitation . . . .”). One passage cited by Patent Owner states the following: with different operating states. For example, a server configured to process financial data may operate at a higher level of criticality during normal business hours, and revert to a lower processing state at another time of day. The aforementioned system may require a higher level of performance from the power converter during such periods of high criticality, which may compromise operating efficiency, but which may admit higher operating efficiency during substantial periods of time in the lower processing state. Ex. 1001, 3:55–64, quoted in PO Resp. 20–21, 47. Patent Owner argues that this passage “illustrates the difference between operational states and system activity at a particular moment” because, according to Patent Owner, “[i]n this example, the system operational state may be in a critical or non-critical state depending on the given performance constraints at a particular time of day.” PO Resp. 20–21; see also PO Resp. 47 (similar argument). We disagree. The ’759 patent passage above effectively correlates processor activity and criticality by saying that, in a period of “high criticality,” the load requires a higher performance level from the power converter than when the load is in a “lower processing state.” Ex. 1001, 3:55–64. Thus, this example shows that a “lower processing state” of a data processing server is a “system operational state” of that server, notwithstanding Patent Owner’s labeling this as a “non-critical state.” See PO Resp. 21. Patent Owner argues that “two processors in two different systems may have the same activity level at some point in time” but may be in different system operational states because, for example, speed is critical with one processor and energy efficiency is critical with the other. PO Resp. 48–49 (citing Ex. 2018 ¶¶ 97–98). Similarly, Dr. Ferrese posits an analogy in which two vehicles are traveling at the same speed but one is carrying a person to a hospital and the other is carrying a family on a road “in a given instant appear to be operating identically,” they “can actually have significantly different system operational states resulting in different preferences in terms of how they are operated and controlled.” Ex. 2018 ¶ 97. These hypotheticals are not persuasive, as they would introduce subjectivity into the claim construction, requiring inquiry into the purpose or intent of a processor’s operation. Furthermore, these hypotheticals are not helpful in resolving the controversy because Petitioner relies on the different activity levels in the prior art as disclosing different system operational states, as discussed below in sections II.D.2.b and II.G.2.a. Thus, we need not opine on whether one activity level of a processor could result in multiple system operational states.” slip op. at 9
Patent outcomesUS 7,675,759 unpatentableClaim construction§ 102 anticipation§ 103 obviousnesscites KSRPatents in suitUS 7,675,759 - Samsung Electronics Co., Ltd / Dell Technologies Inc. et al. v. Mypaq Holdings Ltd.All claims unpatentablePTAB · May 17, 2023 · IPR2022-01134 · APJ Daniel J Galligan · IPR · Final written decision
Claims 1–20 are unpatentable: Chagny anticipates claims 1–12, 14–17, 19, and 20, and renders claims 13 and 18 obvious; remaining grounds were not reached.
RulingsFinal written decision- PTAB / AIA Trials › Joinder §315(c) / SAS all-or-nothingJoinder, grantedGranted
“After institution, Anker filed a motion for joinder and a petition in IPR2022-01134. We joined Anker as a petitioner in this proceeding. Paper 18.” slip op. at 3
- Skill levelSkill level patent owner adoptedDecided for patent owner
“We agree with Patent Owner that some degree of familiarity with power electronics would be necessary for a POSITA given the subject matter at issue, and we understood this to be implicit in part (i) of Petitioner’s definition. To address Patent Owner’s concern, we clarify that a person with a Master of Science in Electrical Engineering or an equivalent field would need experience in power electronics to qualify as a POSITA. We are reluctant to use Patent Owner’s formulation of “some independent expertise in power electronics” (PO Resp. 17 (emphasis added)) because it could be read to include an expert level of skill rather than an ordinary level of skill. Thus, we determine that a POSITA would have had either (i) a Master of Science in Electrical Engineering, or an equivalent field, and experience in power electronics or (ii) a Bachelor of Science in Electrical Engineering or an equivalent field as well as two years of experience in the design of power electronics. We would reach the same determinations on Petitioner’s patentability challenges in §§ II.D–E below even if we adopted Patent Owner’s assessment of a person with a Master of Science degree and “some independent expertise in power electronics (through work or otherwise),” which is a higher level of skill.” slip op. at 7
- Claim Construction › Intrinsic evidence (Phillips canons) › Plain and ordinary meaning to a POSITAPlain and ordinary meaningDecided for petitioner
“system operational state of said load.” As an initial matter, Patent Owner does not direct us to, and we do not find, a definition of “system operational state” of a load in the ’514 patent. As noted above, Patent Owner’s proposed definition is that “the term ‘system operational state’ as it pertains to engineering systems, refers to the way in which the system as a whole is being employed or utilized.” PO Resp. 18 (citing Ex. 2018 ¶ 52). Claim 1, however, recites “a system operational state of said load” (emphasis added), not the system as a whole. Patent Owner’s proposed construction, therefore, is not consistent with the claim language. Patent Owner points to examples disclosed in the ’514 patent in an attempt to narrow the meaning of the claim term and, as further discussed below, to distinguish the prior art. See PO Resp. 18–20 (“The ’514 Patent provides examples of signals indicating system operational states that include signals . . . .” (citing Ex. 1001, 9:14– 27)). But the ’514 patent states that these are non-limiting examples. Ex. 1001, 9:11–23 (“Further examples indicating a system operational state include, without limitation . . . .”). One passage cited by Patent Owner states the following: It should also be taken into account that there are loads with different operating states. For example, a server configured to process financial data may operate at a higher level of criticality during normal business hours, and revert to a lower processing state at another time of day. The aforementioned system may require a higher level of performance from the power converter during such periods of high criticality, which may compromise operating efficiency, but which may admit higher operating efficiency during substantial periods of time in the lower processing state. Ex. 1001, 5:8–17, quoted in PO Resp. 20. Patent Owner argues that this passage “illustrates the difference between operational states and system this example, the system operational state may be critical or non-critical depending on the performance constraints at particular time of day.” PO Resp. 20 (citing Ex. 2018 ¶ 53). We disagree. The ’514 patent passage above effectively correlates processor activity and criticality by saying that, in a period of “high criticality,” the load requires a higher performance level from the power converter than when the load is in a “lower processing state.” Ex. 1001, 5:8–17. Thus, this example shows that a “lower processing state” of a data processing server is a “system operational state” of that server, notwithstanding Patent Owner’s labeling this as a “non-critical” operational state. See PO Resp. 20. Patent Owner argues that “two processors in two different systems may have the same activity level at some point in time” but may be in different system operational states because, for example, speed is critical with one processor and energy efficiency is critical with the other. PO Resp. 21–22 (citing Ex. 2018 ¶¶ 55–56). Similarly, Dr. Ferrese posits an analogy in which two vehicles are traveling at the same speed but one is carrying a person to a hospital and the other is carrying a family on a road trip. Ex. 2018 ¶ 55. Dr. Ferrese states that, even though these two vehicles “in a given instant appear to be operating identically,” they “can actually have significantly different system operational states resulting in different preferences in terms of how they are operated and controlled.” Ex. 2018 ¶ 55. These hypotheticals are not persuasive, as they would introduce subjectivity into the claim construction, requiring inquiry into the purpose or intent of a processor’s operation. Furthermore, these hypotheticals are not helpful in resolving the controversy because Petitioner relies on Chagny’s different activity levels as disclosing different system operational states, as one activity level of a processor could result in multiple system operational states. slip op. at 9
- Novelty / Anticipation (§102) › Anticipation standard (single reference, every element)UnpatentableUnpatentable
“other words, the duty cycle is the “ratio of on-time to the total switching period.” Ex. 1002 ¶ 38. We find that Chagny describes a duty cycle because Chagny discloses that charge switch 220 is turned on and off. See, e.g., Ex. 1004, 5:38–40 (“The opening and closing of the charge and discharge switches 220 and 230 is controlled by the charge and discharge control signals 212 and 214 respectively.”). Patent Owner agrees that charge switch 220 is turned on and off. See Tr. 43:23–44:1 (Q: “Is Patent Owner disputing that there is a conduction time in Chagny that the FET is turned on and off?”; A: “The FET is turned on and off, yes, so that’s correct.”); see also Tr. 45:11–12 (Patent Owner’s counsel stating that “it certainly is turning the FET on and off”). Thus, Chagny discloses that power switch 220 has a duty cycle notwithstanding Patent Owner’s argument that “Chagny does not even discuss duty cycles.” See PO Resp. 33. As to Patent Owner’s argument that “activity input 202 sets the switching frequency, not the duty cycle” (PO Resp. 33), we agree with Petitioner that “[t]here is no requirement that said signal indicating system operational state must ‘set’ the duty cycle.” See Pet. Reply 19–20. Petitioner contends that, because the duty cycle of charge switch 220 determines the output voltage and because that output voltage is then used as feedback to regulate the output voltage (Ex. 1004, 4:63–65), a person of ordinary skill in the art would have understood that the duty cycle of charge switch 220 is controlled “as a function of the feedback from the regulated DC voltage output 295 (i.e., as function of said output characteristic).” Pet. 21 (citing Ex. 1002 ¶ 72; Ex. 1009, 17–18). As to Patent Owner’s argument that Petitioner “cannot rely on knowledge of a POSITA to prove anticipation by Chagny” of ordinary skill in the art would have understood from Chagny’s disclosure. This is appropriate and indeed necessary because “[a]nticipation is established when ‘one skilled in the art would reasonably understand or infer from the prior art reference’s teaching that every claim [limitation] was disclosed in that single reference.’” CRFD Research, Inc. v. Matal, 876 F.3d 1330, 1338 (Fed. Cir. 2017) (quoting Akamai Techs., Inc. v. Cable & Wireless Internet Servs., Inc., 344 F.3d 1186, 1192–93 (Fed. Cir. 2003)). We also credit Dr. Kiaei’s unrebutted testimony that, “for a buck power converter, the output voltage is equal to the input voltage times the duty cycle of the high-side switch (referred to as charge switch [220] in Chagny).” Ex. 1002 ¶ 57. As noted above, Chagny discloses that “controller module 210 receives the regulated DC voltage output 295 as a feedback input for regulating the output of the VRM 200.” Ex. 1004, 4:63– 65, cited in Pet. 21. Thus, we find that Chagny discloses controlling the duty cycle as a function of the output voltage in order to regulate the output voltage as part of the feedback loop.” slip op. at 35
Patent outcomesUS 8,477,514 unpatentableClaim construction§ 102 anticipation§ 103 obviousnesscites KSRPatents in suitUS 8,477,514 - Samsung Electronics Co., Ltd / Dell Technologies Inc. et al. v. Mypaq Holdings Ltd.All claims unpatentablePTAB · May 17, 2023 · IPR2022-00311 · APJ Daniel J Galligan · IPR · Final written decision
Claims 1–20 are unpatentable: Chagny anticipates claims 1–12, 14–17, 19, and 20, and renders claims 13 and 18 obvious.
RulingsFinal written decision- Skill levelSkill level board ownDecided for patent owner
“We agree with Patent Owner that some degree of familiarity with power electronics would be necessary for a POSITA given the subject matter at issue, and we understood this to be implicit in part (i) of Petitioner’s definition. To address Patent Owner’s concern, we clarify that a person with a Master of Science in Electrical Engineering or an equivalent field would need experience in power electronics to qualify as a POSITA. We are reluctant to use Patent Owner’s formulation of “some independent expertise in power electronics” (PO Resp. 17 (emphasis added)) because it could be read to include an expert level of skill rather than an ordinary level of skill. Thus, we determine that a POSITA would have had either (i) a Master of Science in Electrical Engineering, or an equivalent field, and experience in power electronics or (ii) a Bachelor of Science in Electrical Engineering or an equivalent field as well as two years of experience in the design of power electronics.” slip op. at 7
- Claim Construction › Intrinsic evidence (Phillips canons) › Plain and ordinary meaning to a POSITANo construction neededDecided for petitioner
“system operational state of said load.” As an initial matter, Patent Owner does not direct us to, and we do not find, a definition of “system operational state” of a load in the ’514 patent. As noted above, Patent Owner’s proposed definition is that “the term ‘system operational state’ as it pertains to engineering systems, refers to the way in which the system as a whole is being employed or utilized.” PO Resp. 18 (citing Ex. 2018 ¶ 52). Claim 1, however, recites “a system operational state of said load” (emphasis added), not the system as a whole. Patent Owner’s proposed construction, therefore, is not consistent with the claim language. Patent Owner points to examples disclosed in the ’514 patent in an attempt to narrow the meaning of the claim term and, as further discussed below, to distinguish the prior art. See PO Resp. 18–20 (“The ’514 Patent provides examples of signals indicating system operational states that include signals . . . .” (citing Ex. 1001, 9:14– 27)). But the ’514 patent states that these are non-limiting examples. Ex. 1001, 9:11–23 (“Further examples indicating a system operational state include, without limitation . . . .”). One passage cited by Patent Owner states the following: slip op. at 9
- Novelty / Anticipation (§102) › Anticipation standard (single reference, every element)UnpatentableUnpatentable
“Chagny discloses that “activity input 202 [is] indicative of the activity level of the processor 292.” Ex. 1004, 5:9–12. Therefore, Chagny’s activity input 202 is a signal indicating the activity level of a processor, which is within the scope of a signal “indicating a system operational state of said load” under the construction set forth above in section II.C.1. Chagny further explains that “processor 292 loading, usage or activity level will vary depending on the number of instructions executed within a predefined time interval.” Ex. 1004, 4:18–20. Chagny discloses high, medium, and low activity levels. Ex. 1004, 4:31–33. Even applying Patent Owner’s proposed claim construction, Chagny’s low activity level shows how the processor “is being employed or utilized” (PO Resp. 18) consistent with the ’514 patent’s disclosure of a “lower processing state” for a server. Ex. 1001, 5:8–17; see above § II.C.1 (discussing this disclosure). changes the switching frequency of VRM 200 based on activity input 202. See Pet. 19 (citing Ex. 1004, 4:46–49, 4:66–5:18; Ex. 1002 ¶¶ 67–69). In particular, Chagny discloses that frequency selector module 215 of controller module 210 “is operable to receive the activity input 202 . . . and select a switching frequency 216 from a plurality of switching frequencies as an output, which dynamically matches the level of activity of the processor 292.” Ex. 1004, 4:66–5:3; see also Ex. 1004, 5:9–12 (“Thus the controller module 210 dynamically changes the switching frequency 216 of the VRM 200 responsive to the activity input 202 indicative of the activity level of the processor 292.”). Based on Petitioner’s persuasive argument and evidence, we find that Chagny describes “a power converter controller configured to receive a signal from said load indicating a system operational state of said load and control an internal operating characteristic of said power converter as a function of said signal.”” slip op. at 19
- Obviousness (§103) › Motivation to combine / reasonable expectation of successUnpatentableMotivation foundUnpatentable
“We find Petitioner’s obviousness contentions for claims 13 and 18 persuasive. Claim 11 recites that the power system controller is “configured to enable operation of components of a processor system to establish a state of power drain thereof, said power system controller configured to provide a signal to identify operation of said processor system in said state of power drain,” and we find Chagny describes this subject matter for the reasons discussed above in section II.D.4.a. Claims 13 and 18 recite the time at which the signal is provided, specifically “upon startup.” Petitioner’s contention is simply that it would have been obvious for Chagny’s activity including upon startup. Pet. 43–44. Petitioner’s contention is persuasively supported by Dr. Kiaei’s testimony (Ex. 1002 ¶ 140) and Exhibit 1007 (US Patent 6,748,545 B1 (“Helms”)). Patent Owner specifically addresses Petitioner’s evidence for claims 13 and 18 for the first time in its Sur-reply and argues that “it is not clear what the relevance of EX1007 [(Helms)] is.” PO Sur-reply 24. We disagree. Dr. Kiaei explains, relying on Helms, that “it was well known in the art that a microprocessor would send control signals to an adaptive power supply coupled to that microprocessor as soon as the microprocessor was powered up to a level where its control signal was valid.” Ex. 1002 ¶ 140 (citing Ex. 1007, 3:57–64, 4:28–40, 4:50–58, Fig. 3). Helms explains that “[p]ersons of skill in the art are familiar with the power-good signal,” which “is asserted and maintained” after “power is initially applied to a computer system” and when “the voltage rails in the system are stable.” Ex. 1007, 4:50–55. As noted above, Chagny discloses that “activity input 202 may be” slip op. at 43
Patent outcomesUS 8,477,514 unpatentableClaim construction§ 102 anticipation§ 103 obviousnesscites KSRPatents in suitUS 8,477,514 - Samsung Electronics Co., Ltd. v. Mypaq Holdings Ltd.All claims unpatentablePTAB · May 15, 2023 · IPR2022-00308 · APJ Kristina M Kalan · IPR · Final written decision
The Board held claims 1, 4–12, 22, 25–33, 39–43, 46–54, and 56–63 unpatentable as obvious over the instituted combinations of Gilliland and Vista, with additional references for certain grounds.
RulingsFinal written decision- Expert testimonyPetitioner expert creditedDecided for petitioner
“when deformed (or flexed),” we determine that the combination of Gilliland and Vista discloses the “flexibly biased” limitation of the challenged claims. We are persuaded by Petitioner’s arguments that, whether or not the ultimate claim construction requires that the material be flexible (and we have determined that it need not be), Vista discloses the “flexibly biased” limitation. As demonstrated by Petitioner, Vista’s contact terminal 300 depicted in Figure 9 is made of “a conductive material, preferably copper” and includes a “flexible contact spring member 310” made up of first raised portion 390 and second raised portion 340 that are “flexibly coupled at a junction point.” Ex. 1006, 6:33–37, 6:55–59, 6:63–67; Reply 8–10. Patent Owner agrees that Vista’s contact is flexible. See Tr. 13:21–22 (“[T]he flexibility in Vista’s contact is from the junction, which Vista describes specifically as a flexible junction.”). The flexible coupling of the raised portions meets the “flexibly biased” limitation as we have construed it. Furthermore, we find that the raised portions are made of a flexible material (copper), crediting Dr. Kiaei’s testimony that “copper is a flexible material” and that Vista’s contact spring member 310 would have been fabricated in a manner that would provide the spring action that Vista discloses. Ex. 1026 ¶ 26 (citing Ex. 1006, 6:33–37, 6:63–67); see Ex. 1006, 6:63–67 (disclosing “a spring action provided by the flexible contact spring member 310”). Therefore, under our construction, and even under the construction proposed by Patent Owner, we are persuaded by Petitioner’s argument and evidence (Pet. 20–44, 47, 52; Ex. 1004 ¶¶ 84–133, 140, 152) that the Gilliland-Vista combination teaches the “flexibly biased” limitation of independent claims 1, 22, and 43.” slip op. at 25
- Skill levelSkill level board ownOther
“We are reluctant to use the parties’ formulation requiring “expertise” in power electronics because it could be read to include an expert level of skill rather than an ordinary level of skill. Accordingly, we modify the definition set forth in the Institution Decision, so that a person of ordinary skill in the art would have either (i) a Master of Science in Electrical Engineering, Mechanical Engineering or a related field, and experience in the design and/or packaging of power electronics, or (ii) a Bachelor of Science in Electrical Engineering, Mechanical Engineering or a related field as well as two years of experience in the design and/or packaging of power electronics. We further note that the prior art itself demonstrates the level of skill in the art at the time of the invention. Cf. Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001) (explaining that “specific findings on the level of skill in the art . . . [are not required] ‘where the prior art itself reflects an appropriate level and a need for testimony is not shown’” (quoting Litton Indus. Prods., Inc. v. Solid State Sys. Corp., 755 F.2d 158, 163 (Fed. Cir. 1985))).” slip op. at 10
- Claim Construction › Intrinsic evidence (Phillips canons) › Plain and ordinary meaning to a POSITATerm construed petitioner constructionDecided for petitioner
“We adopt the construction of “flexibly biased” as “exerting a force when deformed (or flexed).” In our view, the portion of Patent Owner’s proposed construction requiring “comprising a material” is not necessary to the construction of the phrase “flexibly biased.” Our analysis begins with the claim language. The grammatical nature of the phrase “flexibly biased” within the entire limitation supports construing the phrase without reference to the material that comprises the contact. The claim recites a contact that is “flexibly biased,” so “flexibly biased” is an adjective/adverb combination describing not what the contact is, but how it performs. We next consider the specification. Claim terms of a patent will not be read restrictively “unless the patentee has demonstrated a clear intention to limit the claim scope using ‘words or expressions of manifest exclusion or restriction.’” Liebel-Flarsheim Co. v. Medrad, Inc., 358 F.3d 898, 906 (Fed. Cir. 2004) (quoting Teleflex, Inc. v. Ficosa N. Am. Corp., 299 F.3d 1313, 1327 (Fed. Cir. 2002)). Patent Owner asserts that the ’489 patent “affirms that the flexible contact is flexibly biased because the flexible material creates a bias when contacting the AC power blades to securely couple the PCB to the AC power blades.” PO Resp. 13 (citing Ex. 1001, 5:4–15, 8:35– 45, 11:34–47). We disagree. Patent Owner’s reliance on the ’489 patent’s disclosure that the contacts “comprise a suitable flexible, durable and conductive material” (Ex. 1001, 5:12–13, 8:43, 11:44–45) does not require us to import any “material” limitations into our construction of “flexibly biased.” Rather, the specification discusses the “flexibly biased” property in connection with the ability to “couple” or “securely couple” “with a proximate end of the AC power blades” or “with contact pads.” Ex. 1001, 1:45–47, 5:6–8, 8:37–39, 11:37–39. The construction “exerting a force when deformed (or flexed)” accounts for the specification’s discussion of the term “flexibly biased” and does not impose unnecessary narrowing restrictions on the term. SuperGuide Corp. v. DirecTV Enterprises, Inc., 358 F.3d 870, 875 (Fed. Cir. 2004) (“[A] particular embodiment appearing in the written description may not be read into a claim when the claim language is broader than the embodiment.”). We note that Patent Owner’s expert” slip op. at 12
- Obviousness (§103) › Motivation to combine / reasonable expectation of successMotivation foundReasonable expectation foundUnpatentable
“22, 25–33, 39–43, 46–54, and 56–63 are taught or suggested by Gilliland and Vista, alone or in combination with additional references. Pet. 13–14, 20–90. Patent Owner does not present arguments for the patentability of claims 1, 4–12, 22, 25–33, 39–43, 46–54, and 56–63 apart from its arguments for the patentability of independent claims 1, 22, and 43, and its arguments for the patentability of dependent claims 42 and 63. See PO Resp. We have reviewed the undisputed argument and evidence presented by Petitioner, and we find that the combination of Gilliland and Vista, alone or in further combination with additional references, teaches or suggests the additional limitations of claims 1, 4–12, 22, 25–33, 39–43, 46–54, and 56– 63, and we find that a person of ordinary skill in the art would have been motivated to combine the references in the manner asserted by Petitioner with a reasonable expectation of success. Pet. 13–14, 20–90; Ex. 1004 ¶¶ 83–250. For the same reasons as set forth above for independent claims 1, 22, and 43, we determine that Petitioner has met its burden of proof for the disputed limitations of the challenged claims, whether expressly recited in the independent claims or incorporated by reference in the dependent claims. See 35 U.S.C. 112, para. 4 (2006) (“A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.”). Therefore, based on the full record developed during the trial, we determine that Petitioner has met its burden to demonstrate unpatentability of the challenged claims.” slip op. at 31
Patent outcomesUS 7,978,489 unpatentableClaim construction§ 103 obviousnesscites Phillips · KSR · GrahamPatents in suitUS 7,978,489 - Samsung Electronics Co., Ltd. v. Mypaq Holdings Ltd.All claims unpatentablePTAB · May 15, 2023 · IPR2022-00307 · APJ Kristina M Kalan · IPR · Final written decision
Claims 6 and 10 are unpatentable: claim 6 as obvious over Zverev and Lacap and Liaw and Nam; claim 10 as anticipated by Zverev and obvious over Liaw and Nam.
RulingsFinal written decision- Skill levelSkill level board ownOther
“We are reluctant to use the parties’ formulation requiring “expertise” in power electronics because it could be read to include an expert level of skill rather than an ordinary level of skill. Accordingly, we modify the definition set forth in the Institution Decision, so that a person of ordinary skill in the art would have either (i) a Master of Science in Electrical Engineering, Mechanical Engineering or a related field, and experience in the design and/or packaging of power electronics, or (ii) a Bachelor of Science in Electrical Engineering, Mechanical Engineering or a related field as well as two years of experience in the design and/or packaging of power electronics. We further note that the prior art itself demonstrates the level of skill in the art at the time of the invention. Cf. Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001) (explaining that “specific findings on the level of skill in the art . . . [are not required] ‘where the prior art itself reflects an appropriate level and a need for testimony is not shown’” (quoting Litton Indus. Prods., Inc. v. Solid State Sys. Corp., 755 F.2d 158, 163 (Fed. Cir. 1985))).” slip op. at 10
- Claim Construction › Threshold & procedure › Whether a term needs construction (O2 Micro)Term construed board ownDecided for patent owner
“Patent Owner agrees that “the Board should adopt the construction of ‘monolithically integrated’ as ‘fabricated from a single piece of semiconductor material.’” Sur-Reply 2. We note the ’399 patent’s example of monolithic integration: Figure 3 shows a “monolithically integrated bridge rectifier” (Ex. 1001, 4:24–25), also referred to as “integrated bridge rectifier circuit 106” (id. at 5:36–37) in which “[i]nstead of the four individual diode chips shown in FIG. 2, all four diodes are integrated on one die in silicon-on-insulator (SOI) technology” such that “a compact construction of the individual constituents of the circuit results from the monolithic integration.” Id. at 5:38–44. This contrasts with the “embodiment shown in FIG. 2,” in which “the diodes for the bridge rectifier 106” are “initially present as separate semiconductor chips, also called dies.” Id. at 4:61–64. As quoted by Patent Owner: “In SOI technology, one can realise the four diodes in a single die, so that the additional space requirements for the areas on the leadframe, including the insulation gaps in between, are dropped.” Id. at 3:67–4:3 (quoted in PO Resp. 12). In view of the agreement between the parties, we apply the parties’ proposed joint construction of “monolithically integrated” as “fabricated from a single piece of semiconductor material.” We determine that no other claim term requires express construction. See Vivid Techs., 200 F.3d at 803.” slip op. at 12
- Obviousness (§103) › Motivation to combine / reasonable expectation of successUnpatentableMotivation foundUnpatentable
“persuasively that Zverev’s lead frame, or circuit carrier, when combined with Lacap’s heat-dissipating webs and channels, yields “a metallization of the circuit carrier” that “has cooling areas that are formed for removing heat.” Pet. 48–50. Petitioner’s expert supports Petitioner’s assertions. Ex. 1002 ¶¶ 178–183; Ex. 1035 ¶¶ 14–23. Regarding Patent Owner’s arguments based on Zverev’s Figure 5, we credit the testimony that “Zverev’s Fig. 5 is a cross-section through one plane of the package” and “does not capture how other leads connect to the die pad.” Ex. 1035 ¶ 19. Patent Owner’s arguments derive from a narrow interpretation of Zverev’s Figure 5 cross-section in which the lead frame and pins are depicted with a break between them. An interpretation of Zverev in context, however, indicates that, notwithstanding the slice shown in Figure 5, Zverev’s pins are connected to its lead frame. Petitioner has shown that the understood and accepted manufacturing process of a lead frame would result in the metal structures shown and relied upon to meet this element. Reply 5 (citing Ex. 1035 ¶ 15; Ex. 1036, 23:9–24:5); Tr. 13:21–24; Pet. 9–10; Ex. 1010, 24; Ex. 1011, 21. We also credit the testimony of Petitioner’s expert that a “POSITA would have known that the majority of semiconductor packages connect the die pad to at least one pin to establish a voltage reference” and “it would have been obvious to a POSITA that the die pad would be connected to one (or more) of the leads for this purpose.” Ex. 1035 ¶ 20. Regarding Patent Owner’s argument that Lacap has “attachments to the die pad” that are not part of the lead frame, and therefore the heat transfer channel would not be considered part of the circuit carrier or a metallization of the circuit carrier (PO Resp. 17; Ex. 2020 ¶ 64), we agree with Petitioner that Lacap’s heat transfer channels are part of the lead frame in the Zverev-Lacap combination. Ex. 1035 ¶ 22. Lacap “is fabricated using the same tools and equipment as standard, unenhanced integrated circuit packaging.” Ex. 1008, 4:4–8. We are persuaded that, understanding the manufacturing process behind Lacap, one of ordinary skill in the art “would have understood that the entirety of Lacap’s lead frame, including the heat transfer channels [1020], was formed from a single piece of metal.” Reply 9 (citing Ex. 1035 ¶¶ 15–16, 22). We also agree that “Lacap makes clear that its heat transfer channels are an integral part of the lead frame” rather than “attachments.” Id. We disagree with Patent Owner’s argument that “Lacap’s web 920 cannot be the claimed heat sink because it is attached to pins outside the package.” Sur-Reply 9. Petitioner identifies Lacap’s heat transfer channels 1020 and webs 920 as cooling areas of the lead frame (i.e. circuit carrier) for removing heat. Pet. 50. We see no claim requirement that the recited cooling areas be located inside an integrated circuit package. Even if there were such a requirement, however, Lacap’s heat transfer channels 1020 are shown inside outline 1030 that indicates the limits of the plastic molding 900 in Lacap’s Figure 10. Ex. 1008, 4:32–35, 5:26–28, 5:37–39, Figs. 9, 10 (Figure 9 showing web 920 and plastic molding 900, and Figure 10 showing a top cross-sectional view of Figure 9, showing heat transfer channels 1020 inside outline 1030). Accordingly, Petitioner has met its burden of demonstrating that the combination of Zverev and Lacap meets the limitations of claim 6. We also find that a person of ordinary skill in the art would have combined the teachings of Zverev and Lacap to “improve the thermal characteristics of Zverev’s package,” with a reasonable expectation of success, as asserted by Petitioner. Pet. 48–49. Based on these findings, and for the reasons discussed above, we conclude that the subject matter of claim 6 would have been obvious based on the combined teachings of Zverev and Lacap.” slip op. at 28
- Novelty / Anticipation (§102) › Anticipation standard (single reference, every element)UnpatentableUnpatentable
“persuaded that Zverev discloses the limitations of claim 10. Petitioner demonstrates persuasively that switch T2 and sense MOSFET T3 are monolithically integrated on a single semiconductor chip CH1. Pet. 34–35; Ex. 1002 ¶ 147–148; Ex. 1003 ¶ 47, Fig. 4. Petitioner also demonstrates persuasively that Zverev’s use of the term “chip” (i.e. a single chip or die) as opposed to “package” (i.e., two chips arranged together) shows that the “single semiconductor chip” is synonymous with “single semiconductor die,” i.e., fabricated from a single piece of semiconductor material. Reply 22–23 (citing Ex. 1003 ¶ 18; Ex. 1036, 50:15–51:11 (Patent Owner’s expert acknowledging this distinction)); see also Ex. 1035 ¶¶ 7 (citing Ex. 1001, 4:63–64 as equating semiconductor chips with dies: “separate semiconductor chips, also called dies”), 11. On this point, we credit Petitioner’s expert: the “plain and ordinary meaning” of Zverev’s “integrated on a single semiconductor chip” language “is that there is one piece of semiconductor material (i.e. chip, die) that has the switching transistor, supply device, and/or the sense MOSFET fabricated as an integrated circuit.” Ex. 1035 ¶ 47. In sum, we are persuaded that Zverev “is using ‘chip’ synonymously with ‘die’, i.e., fabricated from a single piece of semiconductor material” rather than synonymously with “package” or any other terminology that would indicate anything other than fabricated from a single piece of semiconductor material. Id. Regarding Patent Owner’s argument that Zverev’s terminology “single semiconductor chip” does not mean “monolithically integrated,” we are persuaded by Petitioner’s evidence and argument to the contrary, as summarized above. Regarding Patent Owner’s argument that nothing about Zverev’s Figure 4 or description shows how Zverev’s cell array is fabricated, we agree with Petitioner’s argument that Zverev’s fabrication process and cell array description show that the additional active components are “monolithically integrated.” Petitioner persuasively argues that Zverev’s “cell array” refers to a “plurality of single transistors” “connected with their load paths and control terminals in parallel to each other,” as described in Zverev, and, therefore, “on a single piece of semiconductor material.” Reply 23–24 (quoting Ex. 1003 ¶¶ 19–20; citing Ex. 1035 ¶¶ 48–49; Ex. 1036, 54:18–55:16). We credit Petitioner’s expert’s reasoning and testimony that, to accomplish Zverev’s configuration of transistors in the same cell array, “these transistors must be on the same piece of semiconductor material.” Ex. 1035 ¶ 49 (citing Ex. 1003 ¶ 20, Fig. 4). We further credit Petitioner’s expert’s testimony that the “details and connections within Figure 4” (Ex. 1003 ¶¶ 47–48) showing and describing the placement of various transistors (i.e. T1, T2, and T3 on chip CH1) teach that T1, T2, and T3 are monolithically integrated on one die. Ex. 1035 ¶¶ 51–52. We have considered Patent Owner’s counterargument that Zverev’s “chip” need not “be fabricated from a single piece of semiconductor material” (Sur-Reply 6–7; Ex. 2020 ¶¶ 70–72), but find this argument lacks supporting evidence and fails to rebut Petitioner’s showing regarding Zverev’s fabrication of a single chip/die with multiple transistors in the same cell array. Accordingly, Petitioner has met its burden of demonstrating that Zverev meets the limitations of claim 6 and, therefore, anticipated claim 6.” slip op. at 38
Patent outcomesUS 7,403,399 unpatentableClaim construction§ 102 anticipation§ 103 obviousnesscites Phillips · KSR · GrahamPatents in suitUS 7,403,399 - PTAB · Apr 12, 2023 · IPR2022-01428 · APJ Daniel J Galligan · IPR · Institution
Instituted IPR of claims 1–34 on all grounds, finding a reasonable likelihood of prevailing on at least one challenged claim.
RulingsInstitution decision- PTAB / AIA Trials › Discretionary denial › Fintiv (parallel litigation)Decided for petitioner
“the PTAB will not deny institution of an IPR or PGR under Fintiv (i) when a petition presents compelling evidence of unpatentability; (ii) when a request for denial under Fintiv is based on a parallel ITC proceeding; or (iii) where a petitioner stipulates not to pursue in a parallel district court proceeding the same grounds as in the petition or any grounds that could have reasonably been raised in the petition.” slip op. at 7
- PTAB / AIA Trials › Institution threshold (reasonable likelihood / more likely than not)InstitutedInstituted
“institute review. The standard for instituting an inter partes review is set forth in 35 U.S.C. § 314(a), which provides that an inter partes review may not be instituted unless the information presented in the Petition and the Preliminary Response shows “there is a reasonable likelihood that the petitioner would prevail with respect to at least 1 of the claims challenged in the petition.” For the reasons explained below, we institute an inter partes review of all challenged claims on all grounds raised in the Petition.” slip op. at 2
- Claim Construction › Threshold & procedure › Whether a term needs construction (O2 Micro)No construction neededNot reached
“For the reasons explained below in section II.E.3.a, we determine that Petitioner has demonstrated a reasonable likelihood of prevailing under the district court’s construction and also under that construction as interpreted by Patent Owner. Because the constructions advocated by Patent Owner do not impact the decision whether to institute, we need not resolve this claim construction issue at this time. See Realtime Data, LLC v. Iancu, 912 F.3d 1368, 1375 (Fed. Cir. 2019) (“The Board is required to construe ‘only those terms . . . that are in controversy, and only to the extent necessary to resolve the controversy.’” (quoting Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999))). 2. “Chip Select Signals,” ”Chip Select Conduits” Claims 6, 11–14, 16–19, and 29–34 recite “chip select signals” or “chip select conduits.” Patent Owner argues that the district court construed the term “chip select signals” and associated “chip select conduits” to “exclude[] situations in which a chip select signal could enable multiple array dies at once” and contends that we should adopt this construction. Prelim. Resp. 23–24 (citing Ex. 2004, 33–34). For the reasons explained below in section II.E.6, we determine that Petitioner has demonstrated a and, therefore, we need not further address this claim construction at this time.” slip op. at 11
- Skill levelSkill level petitioner adoptedDecided for petitioner
“Patent Owner does not dispute Petitioner’s proposed skill level at this time. See Prelim. Resp. 20 (“For purposes of this preliminary response only, Patent Owner applies the skill level proposed by Petitioner.”). To the extent necessary, and for purposes of this Decision, we accept the uncontested assessment offered by Petitioner, with the exception of the qualifier “at least,” which introduces vagueness as to the amount of experience.” slip op. at 9
Claim construction§ 103 obviousnessDiscretionary denialcites KSRPatents in suitUS 8,787,060 - PTAB · Apr 12, 2023 · IPR2022-01427 · APJ Daniel J Galligan · IPR · Institution
The Board instituted IPR on claims 1–20 over all grounds, finding a reasonable likelihood of prevailing on the asserted obviousness challenges.
RulingsInstitution decision- PTAB / AIA Trials › Discretionary denial › Fintiv (parallel litigation)Decided for petitioner
“the PTAB will not deny institution of an IPR or PGR under Fintiv (i) when a petition presents compelling evidence of unpatentability; (ii) when a request for denial under Fintiv is based on a parallel ITC proceeding; or (iii) where a petitioner stipulates not to pursue in a parallel district court proceeding the same grounds as in the petition or any grounds that could have reasonably been raised in the petition. Interim Procedure 9. Here, Petitioner has filed such a stipulation, which provides the following: Samsung stipulates that, if the Patent Trial and Appeal Board institutes an IPR proceeding for U.S. Patent No. 9,318,160 on the grounds presented in Samsung’s petition in IPR2022-01427, Samsung will not pursue an invalidity defense in the Eastern District of Texas action (C.A. No. 21-463-JRG) that the patent claims subject to the instituted IPR are invalid based on grounds that were raised or reasonably could have been raised in the IPR. Ex. 1051. Thus, in light of Petitioner’s stipulation, we do not exercise discretion to deny institution under 35 U.S.C. § 314(a).” slip op. at 7
- Claim Construction › Threshold & procedure › Whether a term needs construction (O2 Micro)No construction neededNot reached
“Pet. 23. Patent Owner argues that we should apply the district court’s constructions for “array die” and “chip select signals.” Prelim. Resp. 21–25. We provide a preliminary analysis of each of these terms below. The parties may address these and any other claim construction issues during the trial, and our final decision including any claim constructions will be based on the full record developed during the trial. 1. “Array Die” The district court construed “array die” as “array die that is different from a DRAM circuit” based on an argument during prosecution of the ’060 DRAM circuits 206A–D in U.S. Patent Application Publication 2008/0025137 A1 (Ex. 1011 (“Rajan137”)). Ex. 2004, 31–32 (citing January 13, 2014 Amendment at 10); see Ex. 1002 (’060 prosecution history), 465 (January 13, 2014 Amendment at 10) (“Rajan does not disclose ‘a plurality of stacked array dies.’ Rajan merely stacks DRAM circuits 206A–D, which are different from array dies.”). Patent Owner argues that we should adopt the district court’s construction so that there is a “consistent construction” between the two proceedings. Prelim. Resp. 23–24. Patent Owner, however, qualifies its position by arguing that “the statements it made during prosecution were specific to Rajan137’s DRAM circuits 206A–D and this should be made clear to the jury through the order instead of having the expert explain it at trial.” Prelim. Resp. 24 n.4 (citing Ex. 2005 (Patent Owner’s objections to the district court claim construction order), 1–2); see Ex. 2005, 2 (“[T]he Court should make clear that the claimed array die is one that is ‘different from Rajan’s DRAM circuits 206A–D.’”). Although Patent Owner appears to walk this qualification back by arguing in its Sur-reply that it withdrew its objections to the district court claim construction (Sur-reply 1–2 (citing Exs. 2010, 2011)), Patent Owner’s position here still appears to be that the term “array die” is one that is different from DRAM circuits 206A–D of Rajan137. For example, in disputing Petitioner’s unpatentability contentions, Patent Owner argues that “the Petition contains no analysis on how or why Kim’s or Riho’s memory dies are different from Rajan137’s DRAM circuits.” Prelim. Resp. 26–27; see also Prelim. Resp. 27 (“Missing from the Petition is any analysis on why the referenced DRAM dies in Grounds 1 and 2 differ from Rajan137’s” slip op. at 9
- Skill levelSkill level petitioner adoptedDecided for petitioner
“contends that a person of ordinary skill in the art “would have had an advanced degree in electrical or computer engineering, or a related field, and two years working or studying in the field of design or development of memory systems, or a bachelor’s degree in such engineering disciplines and at least three years working in the field.” Pet. 5 (citing Ex. 1003 ¶ 60). Petitioner also asserts that “[a]dditional training can substitute for educational or research experience, and vice versa,” and Petitioner identifies particular technology with which a person of ordinary skill in the art would 7 At this stage, Patent Owner does not present any objective evidence of nonobviousness (i.e., secondary considerations) as to any of the challenged claims. Council) industry standards and DRAM (dynamic random access memory) and SDRAM (synchronous DRAM) memory modules. Pet. 5. Patent Owner does not dispute Petitioner’s proposed skill level at this time. See Prelim. Resp. 21 (“For purposes of this preliminary response only, Patent Owner applies the skill level proposed by Petitioner.”). To the extent necessary, and for purposes of this Decision, we accept the uncontested assessment offered by Petitioner with the exception of the qualifier “at least,” which introduces vagueness as to the amount of experience.” slip op. at 8
- Obviousness (§103) › Motivation to combine / reasonable expectation of successMotivation foundInstituted
“Pet. 98–99 (citing Ex. 1016 ¶¶ 40, 45–46; Ex. 1030, 135–36; Ex. 1038, 68; Ex. 1003 ¶¶ 589–606). Petitioner argues that Riho teaches that varying impedances between TSVs that result from, for example, manufacturing processes and chip placement, should be taken into account. Pet. 99–100 (citing Ex. 1016 ¶¶ 55–56, 61); see Ex. 1016 ¶ 61 (discussing that the chip located closest to the control chip has “smaller penetrating through resistance” than a chip farther from the control chip). Petitioner contends that a person of ordinary skill “would have been motivated by Riho2 to account for these variations by selectively activating one or more drivers . . . to achieve the optimal driving strength for each ‘data conduit,’ thus saving power.” Pet. 100 (citing Ex. 1018 ¶¶ 96–97, Fig. 7A; Ex. 1017, 1:22–24, 5:11–14, Fig. 5; Ex. 1003 ¶¶ 598–603); see also Pet. 100–01 (asserting that “[o]ther contemporaneous references confirm that adjusting the driver strength to account for the position of a die in stack was well known at the time” (citing Ex. 1039, code (57), 7:46–49, Fig. 6)). 3. Patent Owner’s Arguments and Our Preliminary Analysis Patent Owner makes two arguments against Petitioner’s challenge to” slip op. at 17
Claim construction§ 103 obviousnessDiscretionary denialcites KSRPatents in suitUS 9,318,160 - Intel Corporation v. Qualcomm IncorporatedAll claims unpatentablePTAB · Mar 21, 2023 · IPR2018-01334 · APJ Daniel J Galligan · IPR · Remand
On remand, the Board held claims 1–9, 12, 16, and 17 unpatentable as obvious over the instituted prior-art combinations.
RulingsRemand decision- RemandOther
“I. INTRODUCTION This case is on remand from the Court of Appeals for the Federal Circuit to address the patentability of claims 1–9, 12, 16, and 17 of U.S. Patent No. 8,838,949 B2 (“the ’949 patent,” Ex. 1001). See Intel Corp. v. Qualcomm Inc., 21 F.4th 801, 814 (Fed. Cir. 2021). For the reasons discussed below, we determine that Petitioner has proven by a preponderance of the evidence that claims 1–9, 12, 16, and 17 are unpatentable. See 35 U.S.C. § 316(e) (“In an inter partes review instituted under this chapter, the petitioner shall have the burden of proving a proposition of unpatentability by a preponderance of the evidence.”).” slip op. at 2
- Claim Construction › Threshold & procedure › Whether a term needs construction (O2 Micro)Term construed board ownDecided for petitioner
“B. Claim Interpretation In this proceeding, we give the claims the broadest reasonable” slip op. at 9
- Obviousness (§103) › Motivation to combine / reasonable expectation of successUnpatentableUnpatentable
Patent outcomesUS 8,838,949 unpatentableClaim construction§ 103 obviousnesscites Phillips · KSR · GrahamPatents in suitUS 8,838,949 - Facebook, Inc. v. Palo Alto Research Center LLCAll claims unpatentablePTAB · Mar 15, 2023 · IPR2021-01434 · APJ John A Hudalla · IPR · Final written decision
Claims 10, 13, and 17 are unpatentable as obvious over Bharat, Kamba, and Willis; the Board did not reach the ground adding Rose.
RulingsFinal written decision- Skill levelSkill level petitioner adoptedDecided for petitioner
“would have possessed at least a bachelor’s degree in electrical engineering or computer science, and two years of work experience in developing client-server applications, including web sites and web applications, and would be familiar with common web technologies, such as HTML and HTTP, and programming languages such as Java and Perl. Pet. 4 (citing Ex. 1002 ¶¶ 9–14). Patent Owner states that it has applied Petitioner’s proposed level of ordinary skill for purposes of this proceeding. PO Resp. 7 (citing Ex. 2005 ¶¶ 40–42). 4 The trial record does not include any evidence of secondary considerations of nonobviousness. We adopt Petitioner’s definition of the level of ordinary skill in the art without the qualifier “at least,” which introduces ambiguity. We are satisfied that this definition comports with the level of skill necessary to understand and implement the teachings of the ’584 patent and the asserted prior art.” slip op. at 8
- Claim Construction › Threshold & procedure › Whether a term needs construction (O2 Micro)No construction neededNot reached
“extensive arguments about how the recited “ranking” that is “assign[ed]” in claim 10 must be a comparative, rather than an objective, measure. PO Resp. 15–18; PO Sur-reply 19–22. Petitioner replies to these arguments from Patent Owner. Pet. Reply 15–19. We need not decide the issue of whether a “ranking” must be comparative because, as discussed below, Petitioner persuasively shows that the asserted prior art teaches the assignment of a comparative ranking. See infra § II.D.4. Because of this, and having considered all of the other arguments in the trial record, we determine that no terms of the challenged claims require explicit construction. See, e.g., Realtime Data, LLC v. Iancu, 912 F.3d 1368, 1375 (Fed. Cir. 2019) (“The Board is required to construe ‘only those terms . . . that are in controversy, and only to the extent necessary to resolve the controversy.’” (quoting Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999))).” slip op. at 10
- Novelty / Anticipation (§102) › Prior-art status of a reference › Printed publication / public accessibilityPrinted publication establishedDecided for petitioner
“testifies that Bharat was “published in the journal Multimedia Systems [and] was publicly available on or shortly after October 21, 1998,” based on a record of the journal in an engineering library at the University of Wisconsin–Madison. Id. ¶¶ 39–46. Patent Owner does not contest the prior art status of Bharat. As noted in our Decision on Institution (see Dec. on Inst. 14), the journal in which Bharat appears (Multimedia Systems) is dated September 1998, and it includes a 1998 copyright date. Ex. 1003, 1–2. Moreover, the copy of the journal referenced in Dr. Hall-Ellis’s declaration and asserted in this case includes a stamp from the University of Wisconsin that is dated October 21, 1998. Id. at 3. In our Decision on Institution, we considered these to be indicators of publication in 1998. Dec. on Inst. 14. We also credited Dr. Hall-Ellis’s testimony regarding public accessibility because it is consistent with other evidence of record. Id. The parties have put forth no further arguments regarding our preliminary findings, and we discern no reason to change them. Thus, we determine that Bharat qualifies as prior art under 35 U.S.C. § 102(b) because Bharat’s publication date in 1998, is more than one year before the earliest possible effective filing date of the challenged claims, which is November 9, 2010. Ex. 1001, code (22); Ex. 1003, 1–3; Ex. 1007 ¶¶ 39–46.” slip op. at 13
- Obviousness (§103) › Motivation to combine / reasonable expectation of successMotivation foundReasonable expectation foundDecided for petitioner
“Patent Owner does not dispute Petitioner’s analysis of the “grouping” step. We are persuaded that Bharat teaches classifying articles into sections. See, e.g., Ex. 1003, 8. We are further persuaded that Willis teaches displaying only summaries and/or headlines of articles. See, e.g., Ex. 1005, 11:11–16, 11:37–43, 12:57–13:3, 13:21–24. Petitioner also has shown persuasively that an ordinarily skilled artisan would have had a reason to implement Willis’s grouping of articles in the Krakatoa system described in Bharat and Kamba: to provide a more effective presentation of news articles that mimics the appearance and organization of a traditional print newspaper. See, e.g., Ex. 1002 ¶¶ 99–100. We additionally are persuaded that an ordinarily skilled artisan would have implemented Willis’s summarized/abridged articles in the system of Bharat and Kamba to provide a more efficient display for the user and to avoid copyright issues.6 See, e.g., id. ¶¶ 103–105. We also are persuaded by Mr. Schmandt’s unrebutted testimony that an ordinarily skilled artisan would have expected success in 6 We find Petitioner’s showing regarding “summary objects” persuasive regardless of whether “summary objects” in Petitioner’s proposed combination includes groups of whole articles or groups of summarized articles/headlines. See Pet. 40–41. implementing Willis’s teachings in the Krakatoa system of Bharat and Kamba because it would have required only routine and conventional computer programming techniques. See, e.g., id. ¶ 106.” slip op. at 30
Patent outcomesUS 8,732,584 unpatentableClaim construction§ 102 anticipation§ 103 obviousnesscites Phillips · KSR · GrahamPatents in suitUS 8,732,584
Holdings, summaries, rulings, issues, outcomes, winners and claim constructions shown for a decision were generated by a large language model reading the opinion. They are a guide to the decision, not the decision. Confirm every one against the court's own text before relying on it. Outcomes read from the patent owner’s side. Party names are extracted from the decision and are missing on about 900 short Director denials and scans, which carry the trial number instead.